Senior Manager – Physical Design

Role Summary:

As a Senior Back End Manager - Physical Design, you will be responsible for leading high-performance ASIC/SoC physical implementation teams delivering complex designs from RTL to GDSII. You will drive execution strategy, build scalable methodologies, manage technical execution across multiple blocks/subsystems, and ensure successful design convergence across advanced technology nodes.

The role requires a strong technical leader with hands-on expertise in physical design, proven ability to manage engineering teams, and experience delivering large-scale silicon programs with aggressive Power, Performance, Area, and Schedule targets.

Key Responsibilities:

Lead and manage a team of Physical Design engineers responsible for implementation and signoff of complex ASIC/SoC designs.

Own overall back-end execution strategy including floorplanning, placement, CTS, routing, timing closure, physical verification, and tape-out readiness.

Drive project planning, resource allocation, execution tracking, risk identification, and mitigation across multiple design milestones.

Provide technical leadership for architecture decisions including hierarchy definition, partitioning strategy, clock architecture, power planning, and implementation methodology.

Collaborate closely with Architecture, RTL, DFT, STA, CAD, Packaging, Foundry, and Program Management teams to achieve successful silicon delivery.

Drive convergence across PPA, timing, power, IR/EM, signal integrity, DRC/LVS, reliability, and manufacturability requirements.

Establish robust execution methodologies, quality checks, automation flows, and best practices across the Back End organization.

Review design quality at key milestones and ensure strong execution discipline through structured reviews and predictable delivery.

Lead debug and resolution of complex design challenges across timing, congestion, power, physical verification, and ECO implementation.

Partner with CAD and EDA vendors to improve flows, evaluate new technologies, and enhance design productivity.

Mentor engineers, technical leads, and future leaders while building a culture of ownership, innovation, accountability, and engineering excellence.

Required Skills & Experience:

15-20 years of experience in ASIC/SoC Physical Design with strong experience managing large Back End implementation teams.

Proven track record of delivering complex SoC designs successfully through tape-out on advanced technology nodes.

Deep expertise in physical implementation flows including floorplan, power planning, placement, CTS, routing, ECO, and signoff closure.

Strong experience with Cadence Innovus based implementation flows.

Expert-level understanding of STA (PrimeTime), IR/EM analysis (Voltus/RedHawk), physical verification (Calibre/ICV), and extraction methodologies.

Hands-on experience with advanced process nodes (5 nm / 3 nm / N3E/N3P) and foundry signoff requirements.

Strong understanding of hierarchical design methodologies, multi-voltage designs, UPF, clock distribution strategies, and MCMM closure.

Experience defining metrics, dashboards, quality checks, and execution processes for predictable project delivery.

Strong scripting and automation mindset using Tcl, Perl, Python, or equivalent languages.

Excellent leadership, communication, decision-making, and cross-functional collaboration skills.

Preferred Skills:

Experience leading full-chip implementation and large subsystem ownership.

Exposure to AI/HPC/networking class SoCs with aggressive performance and power requirements.

Experience building teams, defining organizational processes, and scaling execution methodologies.

Knowledge of ML-driven EDA optimization and next-generation design methodologies is a plus.

Master’s Degree in Electrical Engineering / Electronics / VLSI Engineering preferred.

Key Traits for Success:

Strong technical depth combined with execution leadership.

Ownership mindset with the ability to drive complex programs to closure.

Ability to identify risks early and create structured recovery plans.

Passion for building high-performing teams and mentoring engineers.

Data-driven decision making with focus on quality, predictability, and continuous improvement.

Ability to balance innovation, schedule pressure, and silicon delivery excellence.