Formal Verification Engineer, Google Cloud

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Our mission at Google System Infrastructure is to build the best cloud in the world for Google services and for Google Cloud customers, by solving real world business issues of performance, cost, and scale, utilizing hardware, software, and system solutions. To better serve evolving cloud needs, Google is establishing a team in Israel to develop custom chips for servers.

In this role, you will perform formal verification of design properties of complex ASIC designs. You will collaborate closely with design and verification engineers to define meaningful properties that capture the design intent of a logic block and constraints on its input stimulus. You will also help define and improve design and verification methodologies that allow you to achieve formal verification closure.

Responsibilities

• Plan the formal verification strategy and create the properties and constraints for complex digital design blocks.
• Utilize formal property verification tools combined with formal verification closure techniques to verify properties and apply sign-off to blocks.
• Pioneer and refine formal verification methodologies by systematically embedding AI tools to optimize verification accuracy.
• Architect and implement reusable formal verification components.

Qualifications

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 1 year of experience working on main interconnects, Direct Memory Access (DMA), controllers, and power management.
• Experience working with one or more formal verification tools, such as JasperGold, VC Formal, Questa Formal, or 360-DV.
• Experience capturing design specification in a temporal assertion language such as SystemVerilog Assertions (SVA) or Property Specification Language (PSL).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering or Computer Science.
• Understanding of formal verification algorithms.
• Proficiency with scripting languages, such as Python.