Junior AI SoC Design Verification Engineer, Google Cloud

About the job

In this role, you will join a high-performing Research and Development team dedicated to delivering high-quality silicon. You will partner with cross-functional technical teams throughout the full development lifecycle, taking ownership of quality assurance strategies from the initial concept through final tape-out.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Plan digital design block verification by analyzing specifications and identifying critical scenarios with design engineers.
• Create and enhance constrained-random environments using SystemVerilog and Universal Verification Methodology (UVM), or execute formal verification using SystemVerilog Assertions (SVA) and industry-leading tools.
• Identify and write all types of coverage measures for corner-cases.
• Debug test failures alongside design teams to ensure block correctness.
• Analyze metrics to resolve coverage gaps and drive progress toward tape-out.

Qualifications

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, a related technical field, or equivalent practical experience.
• 1 year of experience using verification components and environments in standard verification methodology.
• Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, or a related field.
• Experience creating and using verification components and environments in a standard verification methodology (e.g., UVM).
• Experience with verification techniques, and the full verification life cycle.
• Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
• Experience with performance verification of ASICs and ASIC components.