Senior Emulation Verification Engineer, Google Cloud

About the job

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
• Develop, execute, and debug full-chip/system on a chip (SoC) tests on emulation platforms.
• Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.
• Define and implement various coverage measures to capture stimulus and corner-case scenarios. Work with software and post-silicon validation teams to reproduce failures on emulation.
• Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out. Explore new verification and emulation methodologies and implement them.

Qualifications

Minimum qualifications:

• Bachelor's degree in Computer Science, Electrical Engineering, or equivalent practical experience.
• 8 years of experience with full-chip/SoC verification (e.g., test definition, creation, execution, and debug).
• Experience developing full-chip/SoC tests using these environments/tools: ASM, C, C++, Perspec, Threadmill, OS, or drivers.
• Experience with execution and RTL/firmware/software debug on hardware emulation (e.g., ZeBu Server, Palladium, Veloce) or FPGA (e.g., EP, HAPS, Protium).
• Experience with design debug tools (e.g., Verdi, Verisium).
• Experience with coding and scripting in C, C++, Perl, TCL, or Python.

Preferred qualifications:

• Experience in embedded software and firmware (e.g., Linux drivers, firmware validation).
• Experience with associated electronic design automation (EDA) tools, automation, and flow enhancements.
• Experience with coding in Verilog/SystemVerilog for design.
• Understanding of SoC architecture and interfaces (e.g., CPU, DDR, PCIe, interconnect, Ethernet, etc.).
• Understanding of register transfer level (RTL) to emulation/field-programmable gate array (FPGA) flows including emulation test benches (e.g., transactors/accelerated verification intellectual properties (VIPs), hybrid, in-circuit emulation).