Senior RTL Engineer, CPU Power

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Own and drive multiple activities related to CPU architecture and system-level energy modeling, competitive performance and power analysis, power optimization, simulation, and rollups.
• Develop novel power analysis techniques, optimization engines, and other tooling solutions to improve battery life analysis and maximize the energy efficiency of our CPU.
• Perform data mining analysis at the RTL and gate-level to define relevant micro-architectural transactions for high-level power estimation.
• Collaborate with the SoC and CPU Power Team on power analysis, projections, and requirements for our CPU, including profiling the power of typical workloads on high traffic websites.
• Perform workload analysis for battery life and define tests for power analysis and optimization.

Qualifications

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in RTL (Register Transfer Level) design using Verilog or SystemVerilog.
• Experience in SoC or CPU/GPU microarchitecture design.
• Experience with low-power digital design methodologies.

Preferred qualifications:

• 3 years of experience in RTL design and low-power design techniques.
• Experience with power management, retention, and DVFS.
• Experience with CPU benchmarking, performance analysis, and competitive study.
• Experience with modern processor microarchitecture and related technologies and algorithms, through academic projects or industry experience.
• Knowledge of programming languages, such as C, C++, and Python.
• Expertise in vendor tools such as PTPX, Ansys Power Artist, Synopsys Prime Power, etc.