Silicon Architect, AI and Infrastructure
Confirmed on the employer's own hiring board on Nov 11, 2026. First seen by Alion on Nov 5, 2026. Google scores B on the Alion truth index.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Silicon Product Architect within the Cloud Silicon Engineering team, you will serve as a technical leader driving end-to-end product architecture for next-generation systems and chips. You will bridge machine learning workloads, system software, and silicon implementation to define differentiated accelerator products that power Google’s technical infrastructure and Cloud AI customers.
In this role, you will own product-level architectural definition from initial concept and pathfinding through specification, silicon execution, and production deployment. You will partner closely with machine learning researchers, compiler and systems software engineers, and cross-functional silicon leads to ensure our chip architectures meet goals across functionality, performance, power, area, cost, reliability, and deployability.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $240000 - $333000 (USD) + 25% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Drive the end-to-end silicon product architecture and roadmap for next-generation accelerators in collaboration with internal AI/ML research teams, software/systems teams, and customers, maintaining a rigorous hardware-software co-design process.
- Define and own product-level chip architectures and top-level specifications, ensuring products achieve goals across functionality, performance, power efficiency, die area/cost, reliability, usability, and fleet deployability.
- Lead architectural pathfinding, trade-off studies, and engaging assessments of emerging AI workloads and semiconductor technologies.
- Set technical direction across key product subsystems to enable rapid and predictable execution of complex server-class ASICs.
- Partner across all phases of silicon development and with compiler/runtime teams to resolve cross-domain bottlenecks and deliver production-ready hardware/software stacks.
Qualifications
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 15 years of experience in computer architecture.
- Experience with high-performance computing (HPC), server processors, GPUs, or machine learning (ML) accelerators.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
- Experience with semiconductor technologies and system-level trade-offs across process nodes, memory subsystems (e.g., HBM/DRAM), interconnects, packaging, and power/performance/area (PPA).
- Experience as the lead product or chip architect across multiple generations of complex data-center AI/ML accelerators, GPUs, or high-performance compute (HPC) silicon.
- Experience driving cross-functional technical alignment across RTL design, physical implementation, verification, thermal/power engineering, and post-silicon validation teams.
- Strong track record of technical influence, mentoring architects, and translating emerging academic and industry AI trends into multi-year silicon product roadmaps.