Staff SerDes Characterization Engineer, Platforms
Confirmed on the employer's own hiring board on Nov 12, 2026. First seen by Alion on Nov 11, 2026. Google scores B on the Alion truth index.
About the job
Our platforms team designs and builds the hardware, software, and networking technologies that power all of Google's services. In this role, you will design and build the systems that are the heart of the computing infrastructure. You will develop from the lowest levels of circuit design to system design and see those systems all the way through to manufacturing. Your work has the potential to shape the machinery that goes into our data centers affecting Google users. As a member of the team, you will manage projects in multiple areas. You will also monitor the performance of vendors working on projects and evaluate new technologies.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $188000 - $274000 (USD) + 20% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Own transmitter and receiver characterization and compliance testing for SerDes interfaces across next-generation compute and networking platforms.
- Lead the development of advanced RX test methodologies, including jitter tolerance, stressed receiver sensitivity, bit error rate, and complex inter symbol interference channel testing. Interpret and map industry standards (IEEE 802.3, OIF-CEI) into rigorous, automated receiver test plans.
- Master and deploy high-bandwidth lab instrumentation, including high-speed arbitrary waveform generators, bit error rate testers, real-time oscilloscopes, and vector network analyzers.
- Collaborate closely with ASIC PHY design, silicon design and validation, and signal integrity teams to root-cause link performance anomalies and optimize TX and RX equalizer and DSP parameters.
- Drive test automation development to maximize test coverage, measurement repeatability, and characterization efficiency.
Qualifications
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
- 6 years of experience in high-speed SerDes validation, physical layer testing, or RF/high-speed measurement.
- 3 years of experience with transmitter and receiver characterization, JTOL testing, and high-speed BERT/AWG instrumentation.
Preferred qualifications:
- PhD degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
- Understanding of SerDes receiver architectures, clock/data recovery (CDR), and adaptive equalization algorithms.
- Demonstrated expertise in developing custom calibration routines for stressed eye test setups and high frequency fixture de-embedding.
- Strong programming skills in Python for automated test execution, statistical data processing, and yield analysis.
- Excellent technical problem solving and cross-functional communication abilities.