Senior ASIC Design Engineer
Confirmed on the employer's own hiring board on Oct 14, 2026. First seen by Alion on Mar 24, 2026.
About Grovf
Grovf is seeking a talented Senior ASIC Design Engineer to join our team in Armenia. We offer a dynamic, learning-driven, and challenging environment where you will contribute to the development of next-generation networking devices for AI infrastructure, pushing the boundaries of performance and power efficiency.
As part of the team, you will play a key role in ASIC development, contributing to micro-architecture definition and leading RTL design efforts, while working closely with verification and architecture teams to deliver high-quality, scalable solutions.
Our collaborative environment fosters growth, innovation, and leadership, providing the opportunity to take ownership, influence technical decisions, and make a meaningful impact.
At Grovf, every individual plays a vital role in the company’s success. If you are looking for a rewarding career, talented colleagues, and an environment that encourages growth, challenge, and leadership, Grovf is the place for you.
Responsibilities
- Lead RTL design for complex, high-performance IP blocks
- Contribute to and influence micro-architecture decisions
- Drive design quality, performance, and scalability (PPA optimization)
- Collaborate closely with verification teams to ensure robust coverage
- Debug and resolve complex design issues across development stages
- Mentor junior engineers and support team growth
- Work cross-functionally with architecture, verification, and physical design teams
Requirements
- 5-8+ years of experience in ASIC/RTL design
- Strong expertise in Verilog/SystemVerilog
- Proven experience designing complex, high-performance IP
- Solid understanding of digital design fundamentals and computer architecture
- Experience with synthesis, timing, and performance optimization
- Strong debugging and problem-solving skills
- Ability to take ownership and drive technical solutions
- Good communication skills and mentoring mindset
Nice to Have
- Experience with high-speed protocols (PCIe, Ethernet, etc.)
- Knowledge of low-power design techniques
- Scripting skills (Python, Tcl)
- Experience working in cross-functional, fast-paced environments
Language Requirement
- English: B2 or higher
If you are interested in
- Designing complex, high-performance ASICs and RTL systems
- Driving architecture and design decisions
- Solving challenging problems related to performance, power, and scalability
- Mentoring engineers and contributing to a strong engineering culture
We would love to hear from you.