Senior HAPS / ZeBu Emulation Engineer
Confirmed on the employer's own hiring board on Oct 18, 2026. First seen by Alion on Apr 14, 2026. Grovf scores B on the Alion truth index.
About Grovf
Grovf is seeking a skilled Senior HAPS/ZeBu Emulation Engineer to join our team. Our work environment is dynamic, educational, and challenging, offering employees the opportunity to contribute to the development of next-generation networking devices for Next generation AI Infrastructure that lead the industry in performance and power efficiency. As part of the team, you will be involved in all stages of ASIC development, including Micro-Architecture, Design, and Verification. Our collaborative environment fosters growth, innovation, and leadership, offering the opportunity to work alongside industry experts and contribute to groundbreaking advancements.
At Grovf, every individual plays a vital role in the company's success. If you're looking for a rewarding career, talented colleagues, and a great environment that fosters growth, challenges, and leadership, Grovf is the place for you.
Role Overview
We are looking for an experienced emulation engineer to drive pre-silicon validation of our next-generation AI datacenter networking ASICs using the Synopsys ZeBu emulation platform. You will own bring-up, compilation, and debug of complex SoC designs, working closely with RTL, DV, and software teams to enable early software development and system-level verification before tape-out.
Core Technical Requirements
Synopsys HAPS platform
- Hands-on experience with HAPS (ZeBu) or ProtoCompiler
- Design partitioning across multiple FPGAs
- HAPS-specific timing analysis & closure
- Interface board and daughter card setup
- HAPS Debug Link / virtual I/O familiarity
FPGA implementation
- Familiarity with FPGA-backed emulation internals
- RTL synthesis and place-and-route concepts
- Clock domain crossing (CDC) management
- Timing constraints & closure fundamentals
- FPGA resource optimization awareness
SoC / RTL knowledge
- SystemVerilog / Verilog RTL reading & debug
- Complex SoC architecture understanding
- High-speed interfaces: PCIe, Ethernet, HBM, DDR
- On-chip interconnects (AXI, CHI, TileLink)
- IP integration and wrapper development
Pre-silicon verification
- Software bring-up on emulator (bare-metal & OS)
- Co-emulation and hybrid simulation flows
- Bug reproduction from simulation to emulation
- Regression and stability testing on platform
- Performance profiling on emulation model
Networking ASIC Domain Knowledge
AI datacenter networking
- High-speed Ethernet (400G/800G) architecture
- Packet processing pipeline concepts
- Network-on-chip (NoC) structures
- Traffic manager & QoS logic
Software & driver bring-up
- Linux kernel / driver development on emulator
- Firmware and bootloader bring-up
- PCIe enumeration and configuration space
- Memory map validation and BAR setup
Tools & Flows
Synopsys ZeBu · Synopsys HAPS / ProtoCompiler · VCS / Xcelium · Verdi / DVE · Synplify Pro · SystemVerilog · Python / Tcl scripting · Git / Perforce · JTAG /ChipScope
Experience & Education
Required
- 5+ years in FPGA emulation or ASIC prototyping roles
- Direct hands-on ZeBu or HAPS platform experience
- Involvement in pre-silicon bring-up of complex SoC designs
- BS in EE, CE, or Computer Science
Preferred
- MS in relevant engineering discipline
- Experience with networking or switch ASICs
- Familiarity with other emulation platforms (Palladium, Veloce)
- Background in AI/ML accelerator silicon
What Makes You Standout
- RDMA / RoCE and UEC protocol familiarity
- Enabled SW team 6+ months before tape-out
- Debugged a complex multi-domain boot failure
- Automated emulation regression flows end-to-end
- Caught critical silicon bugs pre-tape-out on emulator
- Worked fluidly across RTL, DV, and SW teams
Yerevan, Armenia
Full-time
On-site / Remote flexibility
If you want to play a key role in enabling pre-silicon software and system validation for next-generation AI networking ASICs, we’d love to hear from you.