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Location
Hybrid
Seniority
Staff

Confirmed on the employer's own hiring board on Oct 1, 2026. First seen by Alion on Sep 30, 2026.

Overview
Company
Impact
Profile match
HCLTech is a major Indian multinational information technology (IT) services and consulting company headquartered in Noida, Uttar Pradesh. Spun off from the original HCL Group in 1991, it ranks as one of India's largest technology companies alongside firms like TCS, Infosys, and Wipro.

Job Summary

Sub-system level: Hands-on experience to do scan insertion, ATPG coverage improvement, Pattern Generation/Simulation. Should have expertise on Simulation debug No-timing/Timing.

"Sub-system level: Hands-on Experience to do MBIST Insertion, Verification, Pattern generation. Thorough with Diagnostics and Repairability concepts.

Good to have functional & integration knowledge of TAP controllers and JTAG. Working knowledge of JTAG, iJTAG, ICL, PDL etc."

"DFX and DFD feature insertion and verification at SS level. SOC level verification for the same.

QC checks post RTL insertion, SpyGlass, CDC, RDC, VCLP etc."

Capable of doing SOC level verification, Pattern sim and delivery.

Should be able to handle cluster team of 2-3 members.

Must be aware of interface to ATEs, tester hand-off languages/TDL/Verilog and must know to drive/modify test procedures. Desirable to have experience in Post Silicon Debug on Tester.

Good at Communication. Compatible of working Remotely / Hybrid method with multiple sites.

Key Responsibilities

Sub-system level: Hands-on experience to do scan insertion, ATPG coverage improvement, Pattern Generation/Simulation. Should have expertise on Simulation debug No-timing/Timing.

"Sub-system level: Hands-on Experience to do MBIST Insertion, Verification, Pattern generation. Thorough with Diagnostics and Repairability concepts.

Good to have functional & integration knowledge of TAP controllers and JTAG. Working knowledge of JTAG, iJTAG, ICL, PDL etc."

"DFX and DFD feature insertion and verification at SS level. SOC level verification for the same.

QC checks post RTL insertion, SpyGlass, CDC, RDC, VCLP etc."

Capable of doing SOC level verification, Pattern sim and delivery.

Should be able to handle cluster team of 2-3 members.

Must be aware of interface to ATEs, tester hand-off languages/TDL/Verilog and must know to drive/modify test procedures. Desirable to have experience in Post Silicon Debug on Tester.

Good at Communication. Compatible of working Remotely / Hybrid method with multiple sites.

Skill Requirements

Other Requirements

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