Senior Design Lead - BIOS, Test/Interface/Uc Board Design, CPU

Job Summary

seeking an experienced Silicon Validation Board Design Engineer to design, develop, and support hardware platforms used for pre-silicon emulation, post-silicon validation, characterization, and bring-up of complex SoCs/ASICs. The candidate will work closely with silicon design, validation, firmware, and software teams to enable efficient debug and validation of next-generation

Key Responsibilities

Design high-speed validation and characterization boards for ASICs, SoCs, MCUs, and FPGAs.Develop schematics and oversee PCB layout for multilayer boards.Design interfaces including:

• PCIe
• USB
• Ethernet
• DDR/LPDDR
• MIPI CSI/DSI

• Signal & Power Integrity

  • Conduct Signal Integrity (SI) analysis for high-speed interfaces.
  • Perform Power Integrity (PI) simulations and power delivery network validation.
  • Define stack-ups and routing constraints for high-speed PCB designs.
  • Work with PCB vendors and assembly houses for successful board fabrication.

  • Silicon Bring-up & Validation

    • Support first silicon bring-up activities.
    • Develop validation plans and debug methodologies.
    • Investigate silicon, board, and system-level issues.
    • Perform hardware debugging using:
      • Oscilloscope
      • Logic analyzer
      • Protocol analyzers
      • JTAG debuggers
      • Spectrum analyzers

Skill Requirements

B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering,

8+ years (Lead Engineer)

Technical Skills

• Schematic design tools:
  • Cadence OrCAD/Allegro
  • Altium Designer
  • Mentor Graphics Xpedition
• PCB design for 10+ layer high-speed boards.
• DDR3/DDR4/DDR5 or LPDDR design experience.
• Knowledge of PCIe Gen4/Gen5 design considerations.
• Power supply design including PMICs and DC-DC converters.
• JTAG and boundary scan debugging.
• Silicon validation methodologies.

Other Requirements

Lab Skills

• Oscilloscope measurements up to multi-GHz ranges.
• High-speed serial interface debug.
• Power rail characterization and current profiling.