Senior Group Technical Architect

Job Summary

HCLTech is looking for an experienced SI/PI Packaging Design Architect with 18+ years of experience in signal integrity, power integrity and semiconductor package design.

The ideal candidate will have strong expertise in high-speed interface design, package and substrate design, electromagnetic simulation, power delivery network optimization and advanced packaging technologies.

The candidate will work closely with silicon design, package design, PCB, system architecture and manufacturing teams to deliver high-performance semiconductor solutions that meet signal integrity, power integrity, thermal and reliability requirements.

Key Responsibilities

· Lead Signal Integrity (SI) and Power Integrity (PI) analysis for advanced semiconductor packages and high-speed interconnects.

· Drive package and substrate design optimization for high-performance computing, networking, AI/accelerator and SoC products.

· Perform pre-layout and post-layout SI/PI analysis, including crosstalk, insertion loss, return loss, impedance matching and power delivery network (PDN) analysis.

· Lead package-level and package-to-board co-design activities, including bump maps, escape routing, substrate stack-up and interconnect optimization.

· Perform electromagnetic (EM) simulations and analyse high-speed interfaces such as PCIe, DDR, HBM, SerDes, Ethernet and other high-bandwidth interfaces.

· Optimize power distribution networks, decoupling capacitor placement, impedance profiles and simultaneous switching noise.

· Collaborate with package design, RTL/SoC, PCB, thermal, mechanical and manufacturing teams to resolve design challenges.

· Define SI/PI design guidelines, simulation methodologies, sign-off criteria and design review processes.

· Provide technical leadership, mentor engineering teams and drive root-cause analysis for package- and system-level SI/PI issues.

· Support design feasibility studies, technology evaluation, customer reviews and technical proposals.

Skill Requirements

· Hands on experience in semiconductor packaging, signal integrity, power integrity or package/board co-design.

· Strong knowledge of package substrate design, advanced packaging architectures and high-speed interconnect technologies.

· Expertise in SI/PI fundamentals, transmission lines, S-parameters, impedance control, crosstalk, reflections and PDN analysis.

· Hands-on experience with 3D electromagnetic simulation, package extraction and SI/PI sign-off.

· Experience with advanced package technologies such as FC-BGA, 2.5D/3D IC, chiplets and HBM integration.

· Knowledge of high-speed protocols such as PCIe, DDR, HBM, SerDes and Ethernet.

· Proficiency in relevant EDA tools such as Cadence Sigrity, Cadence Clarity 3D Solver, Ansys HFSS, Ansys SIwave or equivalent.

· Understanding of package stack-up, substrate materials, bump/ball assignments, parasitics, thermal constraints and manufacturing considerations.

· Strong problem-solving, technical communication and cross-functional collaboration skills.

Other Requirements

· Experience leading SI/PI architecture, methodology development and technical sign-off for complex semiconductor packages.

· Exposure to advanced packaging for AI, HPC, networking and high-bandwidth memory solutions.

· Experience working with global semiconductor customers and multidisciplinary engineering teams.

-Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related discipline.