Senior Solution Architect
Confirmed on the employer's own hiring board on Oct 30, 2026. First seen by Alion on Oct 23, 2026.
Job Summary
The Foundry Interface Lead will own the technical interface between the semiconductor design organization and the foundry across technology selection, process enablement, tapeout, wafer manufacturing, yield, and first-silicon activities.
The role will ensure effective coordination between internal engineering teams and the foundry, drive resolution of technical and manufacturing issues, and ensure semiconductor programs progress smoothly from technology engagement through first silicon and production ramp.
Key Responsibilities
- Act as the primary technical interface with the foundry for assigned semiconductor programs.
- Drive technology and process selection based on performance, power, area, reliability, cost, and product requirements.
- Coordinate PDK, technology collateral, design rules, standard-cell libraries, and process documentation required by design teams.
- Manage foundry engagement for wafer fabrication, tapeout, mask release, wafer schedules, and silicon delivery.
- Work closely with RTL, physical design, DFT, STA, reliability, packaging, and product engineering teams to resolve foundry-related issues.
- Drive DRC/LVS/PEX and manufacturing-rule closure in collaboration with design and foundry teams.
- Coordinate foundry reviews for signoff, tapeout, mask data preparation, and manufacturing readiness.
- Track wafer fabrication status, engineering lots, process milestones, and first-silicon delivery.
- Establish and maintain foundry technical governance, escalation mechanisms, and issue-tracking processes.
- Support commercial and capacity discussions with the foundry in coordination with procurement and business teams.
- Ensure compliance with foundry NDA, IP, security, and technology-access requirements.
- Maintain risk registers covering technology maturity, PDK readiness, wafer capacity, yield, schedule, and manufacturing risks.
Required Technical Experience
- Strong understanding of ASIC/SoC development and semiconductor manufacturing flows.
Key Responsibilities
- Strong understanding of:
- PDK and technology enablement
- Design rules
- DRC/LVS
- Physical design and signoff
- Tapeout and mask data preparation
- Wafer fabrication - Wafer sort
- Experience working directly with major foundries such as TSMC, Samsung Foundry, GlobalFoundries, UMC, or equivalent.
- Experience with advanced-node and/or mature-node semiconductor technologies.
- Good understanding of PVT/process corners, reliability, electromigration, IR drop, process variation, and manufacturing variability.
- Ability to understand, coordinate, and resolve technical issues across semiconductor design and manufacturing teams.
Leadership & Collaboration
- Strong experience leading cross-functional semiconductor engineering teams.
- Ability to work with foundry technical teams at both engineering and management levels.
- Strong communication and escalation-management skills.
- Ability to drive complex technical issues to closure across multiple organizations.
- Ability to manage multiple semiconductor programs and competing priorities.
- Strong stakeholder-management and relationship-building capabilities.
Skill Requirements
Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics & Communication, Microelectronics, VLSI, Semiconductor Engineering, or a related field.
- 12-20 years of experience in semiconductor/ASIC/SoC development, with significant experience interfacing with semiconductor foundries.
- Proven experience taking multiple silicon programs from technology selection/PDK enablement through tapeout, wafer fabrication, and first silicon.
- Strong knowledge of foundry processes, PDKs, design rules, physical design, DRC/LVS, STA, tapeout, wafer fabrication, yield, and silicon characterization.
Other Requirements
Direct experience working with one or more major foundries such as TSMC, Samsung Foundry, GlobalFoundries, UMC, or equivalent.
- Demonstrated ability to lead cross-functional technical teams and manage technical escalations with foundry engineering teams.
- Strong understanding of semiconductor manufacturing risks, including process variation, yield, reliability, wafer quality, and manufacturing readiness.
- Excellent technical communication, stakeholder management, problem-solving, and negotiation skills.
- Experience with advanced-node technologies and/or complex SoC/ASIC programs is preferred.
- Exposure to chiplet, 2.5D/3D packaging, automotive semiconductor, AI/HPC, networking, or high-performance silicon programs is an advantage.