Senior Technical Architect

Job Summary

ASIC Programs (Switch/NIC) DV

• Lead or contribute to verification of 4-5 ASIC design blocks.
• Develop UVM-based verification environments, sequences, tests, debug, and coverage closure.
• Strong experience in SystemVerilog/UVM.
• Experience with PCIe, UCIe 2.0, and Ethernet protocols.
• Ability to independently own verification deliverables.
• Support customer collaboration in EST timezone.

Required Skills

• Strong SystemVerilog/UVM verification experience
• Knowledge and/or hands-on experience with:
• UCIe 2.0
• PCIe
• Ethernet
• Ability to own design blocks independently and drive verification closure

Responsibilities

The DV team is expected to:

• Own verification of 4-5 design blocks per ASIC
• Develop and execute sequences
• Perform test development and debug
• Drive coverage collection and closure
• Own end-to-end verification execution for assigned blocks
• The customer will own the testbench infrastructure.

Key Responsibilities

1. To design and architect large-scale solutions, ensuring scalability, performance, and security.

2. To train and develop team so as to ensure that there is an adequate supply of trained manpower in the said technology and delivery risks are mitigated.

3. To continuously upskill with cutting-edge tech to deliver high-quality, future-proof solutions meeting client expectations and industry standards.

4. To leverage domain/tech expertise to gather client needs, deliver solutions, and craft a technology strategy aligned with business goals.

Skill Requirements

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Other Requirements

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