SMT Hardware Test Engineer

Job Summary

Client’s Hardware Test Engineering (HWTE) group is looking for a passionate, highly collaborative

vendor for supporting SMT HW managed service. In this engagement, vendor need to provide

SMT Engineering Service Support for Hardware Test, SW, and Program Management. Home/VPG/Accys NPI testing (San Diego position)

Key Responsibilities

• Assist in product DFT (DUT design check, test point presence check, test coverage analysis).

Accordingly, design SMT test stations (interface board with signal conditioning circuit, perform design FMEA). The design shall pass all FBU (fixture bringup checklist) criteria and meet all test coverage requirements without any gaps.

• During POC, EVT, DVT, we will setup Post mortem after each build to review if the build event was adequately supported.
• After the project is handed over to Ops Team at PVT, we will review the entire projects and gather the lesson learn for each project.
• If there is no red flag or issues / concerns highlighted by TDL, then this project is successfully supported.

Skill Requirements

• B.Sc. in EE with 3+ years of experience or M.Sc. in EE + 1 years of relevant experience
• Good understanding analog, digital, and power electronics hardware architectures and design
• Experience in schematic & PCB layout design using Allegro or a similar CAD tool
• Ability to design and debug complex electrical schematics and PCB layouts and propose clear, relevant experiments
• Working knowledge of USB 3.2, USB-PD, Display Port, PCIe, I2C, SPI technologies and protocols, and design
• Good oral & written communication skills - be able to communicate complex engineering concepts clearly and concisely to various cross functional teams and leadership.

Other Requirements

• Prior experience with bed of nails test fixture and designing custom test instruments
• Prior experience of performing parametric data statistical analysis (CPK, GRR etc)
• Prior technical leadership and/or project management experience