Solution Architect
Confirmed on the employer's own hiring board on Oct 23, 2026. First seen by Alion on Oct 23, 2026.
Job Summary
Role Overview:
The Chip Lead is responsible for end-to-end ownership and successful execution of ASIC/SoC programs, spanning architecture alignment, design, verification, implementation, silicon validation, and customer delivery commitments. This role acts as the single point of technical and program accountability, ensuring schedule, quality, and cost objectives are met across cross-functional teams. Lead cross-functional engineering teams (RTL, DV, DFT, Physical Design, and Validation) and ensure your design meets Performance, Power and Area requirements
Key Responsibilities
1. Program Ownership & Execution
- Own full-chip delivery from architecture freeze to silicon bring-up and production release
(Lifecycle Ownership: Govern the IC development flow, overseeing RTL freeze, synthesis, place and route (PnR), static timing analysis (STA), and final GDS tape-out
Silicon Bring-Up: Partner with post-silicon validation and software teams to debug and commercialize the chip)
- Define and manage program milestones, schedules, and critical paths
- Drive execution across design, DV, DFT, PD, AMS, and software teams
- Ensure alignment to customer SoW, KPIs, and acceptance criteria
2. Technical Leadership
- Provide technical direction and decision-making across all chip domains:
o Frontend (RTL, micro-architecture)
o Verification (block-level, subsystem, full-chip)
o Physical Design (PnR, STA, signoff)
o DFT and test strategy
o Power, performance, and area (PPA) optimization
o
3. Technical Competency
- Strong expertise in:
o SoC/ASIC design lifecycle (RTL to GDSII)
o Multi-domain integration (digital, AMS, DFT, PD)
o Low-power design methodologies (UPF/CPF)
- Experience with:
o High-performance SoCs (CPU/GPU/AI accelerators preferred)
o Complex interconnects (NoC/Fabric)
o Architecture & Design: Drive SoC definitions, including micro-architecture, IP selection, memory hierarchies, and NoC fabrics
4. Educational Qualification
Education: B.Tech/M.Tech in Electrical Engineering, Computer Science, or a related field.
Experience: 15+ years of direct industry experience in complex ASIC/SoC design.
Technical Expertise: Deep knowledge of Verilog/SystemVerilog, EDA tools (Synopsys Design Compiler, Cadence), and multi-voltage/low-power design techniques.
Leadership Skills: Proven track record of guiding globally distributed teams from specification to successful tape-out
Key Responsibilities
1. To assess the domain IT landscape assessment and Application portfolio optimization for gap analysis
2. Creation of solution and architectural views (logical| conceptual| development| execution| infrastructure & operations architecture)
3. To study and define system requirements addressing stakeholder| portfolio concerns
4. To ensure knowledge up-gradation and work with new and emerging products/technologies
5. To manage Non Functional Requirement adaption for the solution
6. To contribute towards white/technical papers and knowledge base
Skill Requirements
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Other Requirements
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