Chip Design Integration Engineer

At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You'll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress. As a Hardware Developer for Cognitive Systems, you will design, develop, test, and deliver offerings for Power & Z using the latest technologies. In this role, you will define the physical design and lay out the chip footprint, ensuring that all design constraints are met. Your primary responsibilities will include:

• Design and Develop Offerings: Design, develop, test, and deliver offerings for Power & Z using the latest technologies, defining the physical design and laying out the chip footprint.
• Perform Chip Integration: Interconnect all circuits, arrays, random logic, and I/O on the chip to a given set of ground rules for the silicon technology selected.
• Verify Design Constraints: Perform a series of checks (software runs) to verify that all design constraints are met, utilizing toolsets such as Cadence or other proprietary tools.
• Manage Chip Footprint: Define the physical design and lay out the chip footprint, ensuring effective use of space and meeting design requirements.
• Chip Design Development: Experience with designing, developing, testing, and delivering offerings for Power & Z using the latest technologies, including defining physical designs and laying out chip footprints.
• Chip Integration Engineering: Experience in interconnecting circuits, arrays, random logic, and I/O on chips to meet ground rules for selected silicon technologies.
• Design Constraint Verification: Experience with performing software runs to verify design constraints, utilizing toolsets such as Cadence or other proprietary tools.
• Silicon Technology Application: Experience applying knowledge of silicon technologies to ensure effective chip design and integration.
• Physical Design Optimization: Experience with optimizing physical designs to meet space and performance requirements.
• Familiarity with Proprietary Tools: Experience with Cadence or other proprietary tools for performing software runs to verify design constraints is beneficial.
• Knowledge of Silicon Technologies: Understanding of various silicon technologies and their application in chip design and integration is advantageous.
• Physical Design Principles: Familiarity with principles of physical design optimization to meet space and performance requirements is desirable. India Infrastructure & Technology Hybrid Professional Bangalore, IN Bangalore (0063) IBM India Private Limited Cadence Design Engineering Integration Optimization Physical Design Silicon Software Testing Chip Design Technology Design Principles