Senior Staff Engineer Design

Seasoned DSP Hardware Design expert with 7+ years of experience in taking complex digital signal processing solutions from RTL development to silicon. Strong expertise in Verilog RTL design, fixed-point arithmetic, programmable digital filters, high-throughput data paths, and mixed-signal SoCs. Proven capability in implementing and verifying digital filters within closed-loop control systems, with deep understanding of system stability, phase behavior, and numerical accuracy. Experienced in UVM-based verification, AMBA bus integration, timing closure, CDC, and safety-critical development environments. Combines strong DSP fundamentals with hands-on hardware realization expertise, making them an excellent fit for advanced semiconductor and control-system applications.

Your role

Key responsibilities in your new role

• Expert

  Verilog RTL design for arithmetic data paths: multipliers, accumulators,

  pipelining, resource sharing and time-multiplexing across parallel channels.

• Designing programmable filter hardware - coefficient tables, compact coefficient encodings, and run-time bandwidth reconfiguration.
• Comfortable working alongside UVM-based verification and defining the numerical acceptance criteria (Bit-exact model correlation) Clock domain crossing, reset architecture, and timing closure awareness for high-throughput data paths.
• Register interface and on-chip bus integration (AMBA AHB/APB).

Your profile

Qualifications and skills to help you succeed

• Master’s

  degree in Electrical/Electronic Engineering, Communications Engineering,

  Microelectronics or a related field, with a specialization digital signal

  processing, control engineering or communications.

• A Bachelor’s degree with equivalent demonstrated DSP implementation experience is also welcome
• Minimum 7 years designing digital signal processing hardware in RTL with at least one product taken through to silicon.
• Proven track record implementing digital filters in fixed-point hardware- not only modelling them, but owning the RTL realization, its numerical behavior and its verification.
• Experience where filters sit inside a closed control loop, so that filter bandwidth, group delay and phase behavior directly affect system stability.
• Backgrounds in digital power conversion, motor control, sensor signal chains, audio, or wireless baseband are all relevant.
• Experience in mixed-signal SoCs, working directly with ADC/sensor frontends and understanding how converter behavior shapes downstream processing.
• Automotive or other safety-critical development to ISO 26262 is an advantage

• Deep,

  practical expertise in fixed-point arithmetic and Q-format design: word-length

  and bit-growth analysis, coefficient quantization, rounding and truncation

  modes, overflow and saturation strategy.

• Strong

  command of DSP fundamentals: sampling and aliasing, Z-transform, transfer

  functions, pole/zero placement, frequency response, group delay, and stability

  analysis.

• Familiarity

  with requirements-driven development and traceability tooling such as Jama.

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