EDA AI/ML Layout Engineering Intern
Confirmed on the employer's own hiring board on Oct 11, 2026. First seen by Alion on Sep 29, 2026.
Keysight is at the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~16,800 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do.
Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers.
Responsibilities
At Keysight EDA, we are developing next-generation AI-powered Electronic Design Automation (EDA) technologies to accelerate RFIC and analog IC design. As an EDA AI/ML Layout Engineering Intern, you will contribute to innovative solutions that apply machine learning, optimization, and software engineering to automate layout generation, PCell development, and design space exploration.
Working alongside EDA engineers, AI researchers, and RFIC domain experts, you will help develop intelligent workflows that improve designer productivity and accelerate chip development.
Key Responsibilities
- Develop AI and ML solutions for RFIC and analog layout automation
- Research and prototype machine learning techniques for layout synthesis and design optimization
- Assist in the development of parameterized cells (PCells) and layout generation workflows
- Work on geometric, topological, and rule-aware layout generation techniques
- Contribute to surrogate modeling and design space exploration frameworks
- Build data generation, training, and evaluation pipelines for AI-driven EDA workflows
- Develop software components in Python and potentially C++ under mentorship
- Evaluate AI-assisted design methodologies using real-world semiconductor design problems
- Collaborate with EDA engineers and RFIC designers to validate solutions
Qualifications
Minimum Qualifications
- Currently pursuing a Master's or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, EDA/CAD, Applied Mathematics, or a related technical field
- Strong programming skills in Python
- Familiarity with machine learning frameworks such as PyTorch, TensorFlow, or scikit-learn
- Solid understanding of data structures, algorithms, and object-oriented programming
- Strong analytical and problem-solving skills
- Interest in AI/ML applied to engineering design automation
Preferred Qualifications
- Coursework or research in RFIC Design, Analog IC Design, VLSI Physical Design, EDA/CAD, or Semiconductor Design Automation
- Familiarity with layout automation, PCell development, computational geometry, and design-rule-aware layout generation
- Exposure to surrogate modeling, Bayesian optimization, reinforcement learning, and design space exploration techniques
- Experience with C++, Rust, or performance-oriented software development
- Exposure to software development on Windows or Linux platforms
- Familiarity with Git and modern software development practices
- Interest in AI-assisted schematic generation, layout synthesis, semiconductor design workflows, and next-generation AI-powered EDA tools
- Interest in learning about multithreaded applications and desktop software development
- Curiosity and eagerness to work in an Agile, collaborative team environment
CA Pay Range
Master's: Min $40.32 to Max $43.42
PhD: Min $40.32 to Max $53.67
Relocation is available.
Visa Sponsorship is not available for this position.
Please note, candidates must possess valid work authorization for the duration of the internship. International students requiring work authorization should work with their university to obtain and maintain appropriate CPT or other eligible employment authorization prior to the internship start date.
Careers Privacy Statement ***Keysight is an Equal Opportunity Employer.***
At Keysight EDA, we are developing next-generation AI-powered Electronic Design Automation (EDA) technologies to accelerate RFIC and analog IC design. As an EDA AI/ML Layout Engineering Intern, you will contribute to innovative solutions that apply machine learning, optimization, and software engineering to automate layout generation, PCell development, and design space exploration.
Working alongside EDA engineers, AI researchers, and RFIC domain experts, you will help develop intelligent workflows that improve designer productivity and accelerate chip development.
Key Responsibilities
- Develop AI and ML solutions for RFIC and analog layout automation
- Research and prototype machine learning techniques for layout synthesis and design optimization
- Assist in the development of parameterized cells (PCells) and layout generation workflows
- Work on geometric, topological, and rule-aware layout generation techniques
- Contribute to surrogate modeling and design space exploration frameworks
- Build data generation, training, and evaluation pipelines for AI-driven EDA workflows
- Develop software components in Python and potentially C++ under mentorship
- Evaluate AI-assisted design methodologies using real-world semiconductor design problems
- Collaborate with EDA engineers and RFIC designers to validate solutions
Minimum Qualifications
- Currently pursuing a Master's or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, EDA/CAD, Applied Mathematics, or a related technical field
- Strong programming skills in Python
- Familiarity with machine learning frameworks such as PyTorch, TensorFlow, or scikit-learn
- Solid understanding of data structures, algorithms, and object-oriented programming
- Strong analytical and problem-solving skills
- Interest in AI/ML applied to engineering design automation
Preferred Qualifications
- Coursework or research in RFIC Design, Analog IC Design, VLSI Physical Design, EDA/CAD, or Semiconductor Design Automation
- Familiarity with layout automation, PCell development, computational geometry, and design-rule-aware layout generation
- Exposure to surrogate modeling, Bayesian optimization, reinforcement learning, and design space exploration techniques
- Experience with C++, Rust, or performance-oriented software development
- Exposure to software development on Windows or Linux platforms
- Familiarity with Git and modern software development practices
- Interest in AI-assisted schematic generation, layout synthesis, semiconductor design workflows, and next-generation AI-powered EDA tools
- Interest in learning about multithreaded applications and desktop software development
- Curiosity and eagerness to work in an Agile, collaborative team environment
CA Pay Range
Master's: Min $40.32 to Max $43.42
PhD: Min $40.32 to Max $53.67
Relocation is available.
Visa Sponsorship is not available for this position.
Please note, candidates must possess valid work authorization for the duration of the internship. International students requiring work authorization should work with their university to obtain and maintain appropriate CPT or other eligible employment authorization prior to the internship start date.
Careers Privacy Statement ***Keysight is an Equal Opportunity Employer.***