Sr Engineer, FPGA

Position Overview

We are seeking a Senior FPGA Engineer to design and deliver real-time control logic for our optical amplifier (EDFA) products. In this role, you will design, implement, and verify closed-loop control systems in FPGA, including gain/power control (AGC/APC), pump feedforward and PI feedback, VOA control, transient suppression, optical power monitoring, and laser safety shutdown. You will work closely with optical, hardware, and firmware engineers as well as customers to translate system requirements into stable, measurable, and verifiable hardware behavior.

Key Responsibilities

• Design, implement, and optimize closed-loop control algorithms in FPGA, including feedforward and PI control of pump lasers, VOA control, gain/power control modes, and bumpless transfer between modes.
• Develop control and signal processing models in MATLAB or Python (loop stability, discretization, filter design, fixed-point quantization effects) and translate them into efficient, bit-accurate RTL implementations.
• Design the PD optical power monitoring chain, including ADC interfaces, anti-aliasing and digital filtering, dB/mW conversion, calibration, Tidemark peak hold, and alarm detection.
• Develop on the Xilinx Zynq SoC platform, including PS-PL interfaces (AXI4-Lite/AXI4, register maps, interrupts, and DMA as needed), and define the hardware/software partitioning together with firmware engineers.
• Achieve timing closure and fit designs into resource-constrained devices; develop self-checking testbenches; perform board-level debugging using ILA and lab instruments.
• Verify performance in the lab using tunable light sources, optical spectrum analyzers (OSA), variable optical attenuators, optical power meters, and oscilloscopes, and analyze transient, accuracy, and stability test results.
• Analyze customer specifications and test reports, identify root causes (FPGA, firmware, hardware, or optics), propose solutions, and document findings.

Qualifications

• Bachelor's degree or higher in Electrical Engineering, Control Engineering, Telecommunications, or a related field.
• Strong foundation in control theory, including PID/PI design, stability analysis, discretization of continuous-time controllers, anti-windup and saturation handling, and step/transient response tuning.
• 5+ years of hands-on FPGA development experience (Verilog/SystemVerilog/VHDL), with a track record of delivering products to volume production, and proven skills in timing closure and board-level debugging.
• Proficiency with the Xilinx Zynq (or Zynq UltraScale+) platform, including a solid understanding of PS-PL architecture, AXI interfaces, and register design, as well as proficiency with EDA tools such as Vivado, ModelSim, and Lattice Diamond.
• Strong hands-on lab skills, with proficiency in using oscilloscopes and optical communication test equipment (light sources, OSA, optical attenuators, optical power meters).
• Ability to read and discuss technical specifications in English and to communicate clearly with customers and cross-functional teams.

Preferred Qualifications

• Hands-on FPGA project experience with EDFA, Raman, or other optical amplifiers.
• Background in optical communications, including knowledge of amplifier fundamentals (gain, ASE, NF, tilt), photodiodes and logarithmic amplifiers, and optical safety mechanisms (APR/ALS).
• System-level understanding of DWDM networks, such as transient control during channel add/drop events and the behavior of cascaded amplifiers.
• Experience with mixed-signal front ends (ADC drivers, anti-aliasing filters) and hardware/software co-debugging.

What We Value

• Ability to work independently and drive issues to closure with minimal supervision.
• Self-motivated and accountable, with a genuine passion for the optical communications industry.
• Rigorous, evidence-based thinking, with a habit of validating conclusions through code, simulation, and measurement.
• Innovative mindset and the ability to solve problems within real-world constraints such as resources, timing, cost, and schedule.
• Fast learner with clear written and verbal communication skills.