Physical Design Engineer

The Physical Design Engineer will be responsible for the full-chip and/or block-level physical implementation of complex digital, mixed-signal, or RF integrated circuits from RTL to GDSII (the final manufacturing data). This role requires expertise in design methodologies to achieve optimal performance, power, and area (PPA) targets while ensuring manufacturability.

Key Responsibilities:

• Physical Implementation Flow: Own and execute all phases of the physical design flow, including:
• Synthesis (RTL to Netlist).
• Floorplanning and Partitioning (defining block boundaries, pin placement, and power grid planning).
• Power Rail/Grid Design and analysis (EM/IR Drop).
• Place and Route (placement of standard cells and macro blocks, followed by signal routing).
• Clock Tree Synthesis (CTS): Design and optimize the clock network for minimal skew and latency.
• Timing Closure: Perform Static Timing Analysis (STA), identify critical paths, and implement design optimization techniques (e.g., buffering, sizing, ECOs) to meet all frequency and timing constraints (setup/hold).

Education:

• Bachelor's or Master's degree in Electrical Engineering (EE), Electronics Engineering, VLSI, or a related field.

Technical Skills & Experience:

• Experience: 5+ years of experience in physical design, with a proven track record of tape-outs in advanced process nodes (e.g., 16nm, 7nm, 5nm, or lower).
• EDA Tools: Expert proficiency with industry-standard Electronic Design Automation (EDA) tools from vendors like Synopsys (e.g., Fusion Compiler, ICC2, Primetime), Cadence (e.g., Innovus), or Mentor Graphics.

Soft Skills:

• Excellent analytical, debugging, and problem-solving skills.
• Strong verbal and written communication skills.
• Ability to work effectively in a team environment and collaborate across different engineering disciplines.

Employment Type:

Permanent

Skills

Floor Planning, Physical Design, STA, Static Timing Analysis