ASIC & FPGA Design Engineer - E2

Standard Job Description

What We're Doing

At Lockheed Martin, we are passionate about innovation and integrity. We believe that by applying the highest standards of business ethics and forward-thinking, everything is within our capacity - and yours as a Lockheed Martin employee. Lockheed Martin values your skills, training, education, and background!

The Work

As an ASIC/ FPGA Engineer you will;

• Perform complex FPGA firmware architecture and/or custom digital board designs.
• Design digital signal processing, messaging, control, and high-speed communications.
• Interface and collaborate with program leadership and teammates on a regular basis.
• Estimate, break down and plan work for their firmware team.

Who We Are

Our team comprises a diverse group of highly motivated and dedicated technical professionals. We foster a collaborative environment that values teamwork and creativity.

Syracuse, NY is a vibrant and diverse city located in the heart of upstate New York. With a rich history and culture, there's always something to see and do in Syracuse. From the historic architecture and neighborhoods to the thriving arts scene and delicious food, there's something for everyone here.

Who You Are

You understand how the many different pieces of a system work together. Our products involve hundreds of people, processes, and systems, and you’ll help determine the ones that are relevant to your analysis and how they fit together.

A level 2 employee is typically early to mid-career and has 2 to 5 years of professional experience.

Why Join Us

Our team puts a high value on work-life balance. Striking a healthy balance between your personal and professional life is crucial to your happiness and success here, which is why we aren't focused on how many hours you spend at work or online. Instead, we're happy to offer a flexible schedule so you can have a more productive and well-balanced life both in and outside of work.

Develops, designs, verifies, and documents Application-Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) development. Determines architecture design, logic design, and system simulation. Assignments include the analysis of all aspects from high-level design to synthesis, place and route, and timing and power utilization. Typically uses specialized equipment to establish operation data, conduct experimental tests, and evaluate results.

Lockheed Martin Rotary and Mission Systems (RMS) in Syracuse, NY is seeking a full-time Mid Career Firmware Engineer (FPGA Design). In this role, you will support design and architecture development, implement FPGA designs and integrate and troubleshoot designs.

Basic Qualifications

Candidate must possess a BS in an engineering discipline (e.g. Mechanical, Electrical, and/or Computer Engineering)

FPGA architecture and design, with applied knowledge of either the Xilinx, Intel or Microsemi FPGA devices and their associated application environments.

Possess technical expertise to implement designs without appreciable direction.

Exercises considerable latitude in determining technical objectives, using current technology such as FPGAs, Microprocessors, DSPs, and Interface Controllers.

Successful candidate may develop technical solutions to complex problems which require the regular use of ingenuity and creativity applied to FPGA design.

The candidate should possess excellent oral, written, and presentation skills.

Desired Skills

Successful candidate should possess the ability to efficiently perform on multiple tasks simultaneously and guide the successful completion of major programs and may function in a project leadership role.

Strong working knowledge of digital signal processing functions, specific to radar and electronic warfare capabilities, including digital receivers and exciters.

Extensive VHDL firmware programming capability, and having applied that knowledge on an FPGA device (Xilinx, Intel, Microsemi).

Having utilized Xilinx Vivado, Intel Quartus, or Microsemi Libero development platforms to successfully build and test an executable hardware implementation of code which they have written.

Use of the Mentor Questa HDL simulator, including UVM verification techniques.

Experience with MATLAB modeling is a plus.

Higher level code development, including Nvidia CUDA, OpenCL, Simulink HDL Coder, and Xilinx System Generator are also a plus.

Pay Information

Full-Time Salary Range: $81100.00 - $150500.00

At Lockheed Martin, we know mission success starts with taking care of our people. Our Total Rewards program is designed to attract top talent, support your well-being, and help you grow-both professionally and personally.

The salary range for this position is as listed on the requisition. Please note that the salary information listed is a general guideline only. Lockheed Martin considers factors such as (but not limited to) scope and responsibilities of the position, candidate's work experience, education/ training, key skills as well as market(work location) and business considerations when extending an offer.

Benefits offered: Medical, Dental, Vision, Flexible work arrangements and schedules (e.g., 4x10), 401(k) match, Paid time off, Holidays, Parental Leave, EAP, Flexible Spending Accounts, Education Assistance, Life Insurance, Short-Term Disability, and Long-Term Disability.

• Annual short-term and/or long-term incentive compensation programs may be offered depending on the position. Payments under these annual programs are not guaranteed and can vary from year to year and are tied to a range of performance metrics.
• For (Washington state applicants only) Non-represented full-time employees: accrue at least 10 hours per month of Paid Time Off (PTO) to be used for incidental absences and other reasons; receive at least 90 hours for holidays. Represented full time employees accrue 6.67 hours of Vacation per month; accrue up to 52 hours of sick leave annually; receive at least 96 hours for holidays. PTO, Vacation, sick leave, and holiday hours are prorated based on start date during the calendar year.