ASIC & FPGA Design Engineer Sr Stf - E5
Confirmed on the employer's own hiring board on Nov 14, 2026. First seen by Alion on Nov 13, 2026. Lockheed Martin scores A on the Alion truth index.
Standard Job Description
Please join us as an ASIC & FPGA Verification Engineer, where you will be working within the central ASIC & FPGA Engineering division for Lockheed Martin Space. You will have the opportunity to support over 50 different programs and research and development (R&D) efforts. Your work will affect technology across military space, civil space, commercial space, missiles, missile defense platforms, satellite surveillance platforms, deep space exploration, and manned flight missions.
IN THIS ROLE, YOU WILL:
Work with low SWaP, radiation hardened, space rated devices.
Devise a unique verification plan for a given design.
Use SystemVerilog and Universal Verification Methodology (UVM) to verify a design in a Linux-based high-performance computing environment.
Develop requirements, test cases, build test benches, generate reports, and document verification results.
Work with an independent design team to document and resolve bugs found in the design.
Support all aspects of ASIC and FPGA development, to include architecture, design, and analysis.
Support technical reviews, and be able to present to internal and external stakeholders.
The information below reflects the standard job description for this position:
Develops, designs, verifies, and documents Application-Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) development. Determines architecture design, logic design, and system simulation. Assignments include the analysis of all aspects from high-level design to synthesis, place and route, and timing and power utilization. Typically uses specialized equipment to establish operation data, conduct experimental tests, and evaluate results.
Basic Qualifications
- Bachelor of Science or higher from an accredited college in Electrical Engineering or related discipline, or equivalent experience/combined education.
- Experience in the verification of FPGA and/or ASIC devices.
- HDL programming experience with VHDL, Verilog, and/or SystemVerilog.
- Willing and able to obtain and maintain a DoD Secret clearance, thus US Citizenship is required for this position.
Desired Skills
- Masters or PhD highly preferred.
- Experience in ASIC / FPGA life cycle (architecture, design, simulation, verification, validation, integration & test).
- FPGA/ASIC design experience is a plus.
- Experienced in scripting such as Perl, TCL, Python.
- Experience developing test cases based off given requirements.
- Experience building test benches for FPGA / ASIC designs to provide randomized stimulus.
- Experience identifying and implementing necessary test exclusions.
- Experience generating coverage reports (code and functional)
- Experience or knowledge of MS Project, JIRA.
- Experience leading projects of multiple engineers, managing schedules. prioritizing work and actively communicating with internal or external stakeholders.
- Knowledge of space-grade/qualified FPGAs and ASICs.
- Experience with Earned Value Management System (EVMS).
- Experience mentoring junior engineers.
- Proficient in AI prompting as it applies to this position and practice.
Pay Information
Full-Time Salary Range: $185400.00 - $344400.00
At Lockheed Martin, we know mission success starts with taking care of our people. Our Total Rewards program is designed to attract top talent, support your well-being, and help you grow-both professionally and personally.
The salary range for this position is as listed on the requisition. Please note that the salary information listed is a general guideline only. Lockheed Martin considers factors such as (but not limited to) scope and responsibilities of the position, candidate's work experience, education/ training, key skills as well as market(work location) and business considerations when extending an offer.
Benefits offered: Medical, Dental, Vision, Flexible work arrangements and schedules (e.g., 4x10), 401(k) match, Paid time off, Holidays, Parental Leave, EAP, Flexible Spending Accounts, Education Assistance, Life Insurance, Short-Term Disability, and Long-Term Disability.
- Annual short-term and/or long-term incentive compensation programs may be offered depending on the position. Payments under these annual programs are not guaranteed and can vary from year to year and are tied to a range of performance metrics.
- For (Washington state applicants only) Non-represented full-time employees: accrue at least 10 hours per month of Paid Time Off (PTO) to be used for incidental absences and other reasons; receive at least 90 hours for holidays. Represented full time employees accrue 6.67 hours of Vacation per month; accrue up to 52 hours of sick leave annually; receive at least 96 hours for holidays. PTO, Vacation, sick leave, and holiday hours are prorated based on start date during the calendar year.