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Salary
≈ $62k – $137k per year (Estimated)
Location
In office (Hsinchu)
Seniority
Architect

Confirmed on the employer's own hiring board on Sep 25, 2026. First seen by Alion on Aug 3, 2026. MediaTek scores C on the Alion truth index.

Overview
Company
Impact
Profile match
MediaTek Inc. is a global fabless semiconductor company specializing in system-on-chip (SoC) architectures and digital multimedia processing technologies. The enterprise designs and markets integrated circuits for smartphones, smart home devices, IoT hardware, wireless connectivity solutions, automotive electronics, and custom AI chips for edge and cloud applications. Headquartered in Hsinchu, Taiwan, the organization operates an international network of research, development, and sales offices serving original equipment manufacturers (OEMs) and technology brands worldwide.
Role Summary

We are looking for a visionary Datacenter Compute Platform Architect to enable our cutting-edge silicon on the platform. While our SoC architects focus on what goes inside the chip, you will be the owner of the system that surrounds it.

In this role, you will define the end-to-end server platform architecture, ensuring our CPUs operate at peak performance, efficiency, and reliability within cloud infrastructure. You will drive hardware specifications spanning power delivery, thermal management, memory topologies, high-speed I/O routing, and system management. You will work closely with internal silicon teams, firmware engineers, and external OEM/ODM partners and hyperscale customers to bring next-generation compute platforms from concept to mass deployment.

Key Responsibilities

  • Platform Architecture Definition: Define the compute system architecture (workstation, 1U/2U, multi-node, OCP form factors) surrounding our Datacenter compute SoC.
  • Power & Thermal Management: Architect system-level power delivery networks (PDN/VRM specs) and collaborate on advanced thermal solutions (air and liquid cooling) to meet strict datacenter TDP constraints.
  • High-Speed I/O & Memory: Define system-level topologies and routing guidelines for high-speed interfaces, including LP/DDR5/6, PCIe Gen 5/6, and CXL. Ensure Signal Integrity (SI) and Power Integrity (PI) targets are met at the board level.
  • Server Management & Security: Define architectures for Baseboard Management Controllers (BMC), OpenBMC integration, hardware Root of Trust (RoT), and system-level security (e.g., SPDM, TPMs).
  • Firmware/OS Co-Design: Partner with SoC silicon, BIOS/UEFI, OS, and firmware teams to define ACPI tables, RAS (Reliability, Availability, and Serviceability) flows, and power management states.
  • Ecosystem & Partner Enablement: Act as the primary technical interface for Tier-1 ODMs, OEMs, and Cloud Service Providers (CSPs) to ensure successful platform design, validation, and deployment.

#LI-JK1

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