Datacenter Compute SoC Perf/Power Modeling Architect

MediaTek’s Data Center team is at the forefront of innovation, driving the development of cutting-edge technologies that power the world's most advanced data centers. We are a dynamic group of system architects, packaging technology developers, and SoC design experts dedicated to creating high-performance, efficient, and reliable solutions. Our team collaborates closely to push the boundaries of technology, ensuring optimal performance, power efficiency, and scalability for data center applications. Join our Data Center team and be a part of the technological revolution that is shaping the future of data centers. If you are passionate about innovation and have the expertise to drive strategic technology development, we would love to hear from you.

Role Summary

We are looking for a highly skilled Datacenter Compute SoC Performance Modeling Engineer. In this role, you will be at the forefront of defining our next-generation cloud and datacenter processors. You will develop and maintain high-speed, cycle-accurate, and transaction-level architectural simulators to evaluate design trade-offs, identify performance bottlenecks, and project system performance across a wide range of datacenter workloads.

You will collaborate closely with CPU/Compute core architects, SoC architects, IP architects, workload characterization teams, and RTL designers to ensure our silicon delivers industry-leading performance-per-watt and scales efficiently to meet the demands of modern hyper-scale infrastructure.

Key Responsibilities

• Simulator Development: Design, develop, and maintain cycle-accurate and transaction-level performance models (C++/SystemC) for multi-core datacenter SoCs, including CPU cores, memory subsystems, interconnects (NoC), and high-speed I/O (PCIe/CXL).
• Workload Analysis & Profiling: Analyze and characterize cloud-native workloads, microservices, databases, and AI/ML data processing pipelines to drive architectural requirements.
• Performance Exploration: Conduct what-if analyses and architectural design sweeps to optimize cache sizes, memory bandwidth, latency, interconnect topologies, and core counts.
• Bottleneck Identification: Identify micro-architectural and system-level performance bottlenecks and propose innovative hardware or software solutions.
• RTL & Silicon Correlation: Work with RTL verification and post-silicon validation teams to correlate the performance model against RTL simulations, emulators, and actual silicon, ensuring model accuracy.
• Tooling & Infrastructure: Build and enhance tracing tools, data visualization dashboards, and automated performance regression pipelines using Python and data analysis libraries.

Location: open to San Jose, San Diego, Portland and Austin

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