745,032open jobs
44,747companies
107,631added this week
Browse all
Salary
≈ $39k – $93k per year (Estimated)
Location
In office (Bengaluru)
Seniority
Staff

Confirmed on the employer's own hiring board on Sep 24, 2026. First seen by Alion on Dec 11, 2025.

Overview
Company
Impact
Profile match
MediaTek Inc. is a global fabless semiconductor company specializing in system-on-chip (SoC) architectures and digital multimedia processing technologies. The enterprise designs and markets integrated circuits for smartphones, smart home devices, IoT hardware, wireless connectivity solutions, automotive electronics, and custom AI chips for edge and cloud applications. Headquartered in Hsinchu, Taiwan, the organization operates an international network of research, development, and sales offices serving original equipment manufacturers (OEMs) and technology brands worldwide.
Key Responsibilities:

1. Develop and implement comprehensive verification plans for HBM4/4e IP and Subsystem.

2. Create and maintain testbenches, test cases, and verification environments using System verilog and UVM methodology.

3. Perform functional verification of RTL designs, including simulation, debugging, and coverage analysis.

4. Collaborate with design engineers to understand design specifications and requirements for IP and subsystems.

5. Identify and resolve design and verification issues, ensuring high-quality and robust designs.

6. Generate and analyze verification metrics to track progress and ensure coverage goals are met.

7. Participate in design and verification reviews, providing technical expertise and insights.

8. Stay updated with the latest verification technologies and methodologies and apply them to improve verification efficiency and effectiveness.

9. Mentor junior verification engineers and provide technical guidance.

Free account
Stop reading job ads. Get the ones that fit.
One free account turns this page into a shortlist built around your stack, your level and your pay.
Match on every job. Stack, seniority, pay and location, scored against your profile.
745,032 open roles. Read straight off company career pages, refreshed every day.
Unlimited applications. Every one you send is tracked in one place, on-site or on a company board.
3 tailored CVs a month. Rewritten for the exact job you are applying to. Included free.
Create a free account Continue with Google
Free forever. No card. Under a minute.

Your match

How well do you fit this role?
Two answers are enough for a real match. No account needed.
Check my fit
Answers stay in this browser until you create an account.

Recommended for you based on this role

Hardware
Similar stack
Same company
Bengaluru
RTL Design Lead 8 hours ago
≈ $37k – $89k per year (Estimated) • In office • Bengaluru
Python
Verilog
SystemVerilog
Perl
Apply
≈ $37k – $88k per year (Estimated) • In office • Full-Time • 8+ years exp • Bengaluru
Verilog
Chips/EDA
Synopsys Design Compiler
Synopsys SpyGlass
Management
Agile
Scrum
Apply
ASIC Engineer Staff 1 month ago
≈ $43k – $88k per year (Estimated) • In office • Full-Time • 10+ years exp • Bachelor's Degree • Bengaluru
Apply
≈ $50k – $101k per year (Estimated) • In office • Full-Time • 6+ years exp • Bengaluru
Python
AI/ML
AI Agents
Chips/EDA
Cadence Tempus
Apply
≈ $49k – $98k per year (Estimated) • In office • Full-Time • 6+ years exp • Bachelor's Degree • Bengaluru • Hyderabad
Apply
≈ $46k – $99k per year (Estimated) • In office • 3+ years exp • Bachelor's Degree • New Taipei
Python
Verilog
C++
SystemVerilog
Chips/EDA
UVM
Apply
$87k – $137k per year • In office • Full-Time • 8+ years exp • Bachelor's Degree • Leixlip
SystemVerilog
AI/ML
OpenCV
TensorFlow
PyTorch
Edge AI
DevOps
CI/CD
Git
Chips/EDA
UVM
Formal Verification
Apply
$37k per year • In office • Full-Time • Moscow
Verilog
SystemVerilog
MATLAB
MATLAB
Simulink
Apply
In office
Chips/EDA
UVM
Apply
≈ $28k – $61k per year (Estimated) • In office • 4+ years exp • Bengaluru
Verilog
SystemVerilog
VHDL
Chips/EDA
Siemens QuestaSim
Siemens ModelSim
Xilinx Vivado
Libero SoC
Management
Slack
Apply
RTL Design Lead 8 hours ago
≈ $37k – $89k per year (Estimated) • In office • Bengaluru
Python
Verilog
SystemVerilog
Perl
Apply
≈ $33k – $72k per year (Estimated) • In office • 4+ years exp • Master's Degree • Bengaluru
Apply
≈ $36k – $77k per year (Estimated) • In office • 5+ years exp • Bengaluru
SystemVerilog
Chips/EDA
UVM
Apply
Formal Verification 8 hours ago
≈ $34k – $74k per year (Estimated) • In office • 5+ years exp • Bachelor's Degree • Bengaluru
Python
Verilog
C++
SystemVerilog
VHDL
Perl
SystemC
Chips/EDA
UVM
Formal Verification
Synopsys VC Formal
Apply
≈ $29k – $63k per year (Estimated) • In office • 3+ years exp • Bengaluru
Python
Verilog
C++
SystemVerilog
Perl
SystemC
DevOps
Linux
Unix
Chips/EDA
UVM
Apply
≈ $28k – $60k per year (Estimated) • In office • Full-Time • Master's Degree • Bengaluru
Apply
≈ $33k – $72k per year (Estimated) • In office • Full-Time • 10+ years exp • Master's Degree • Bengaluru
Apply
≈ $34k – $73k per year (Estimated) • In office • 5+ years exp • Bengaluru
Python
Verilog
C++
Perl
Apply
≈ $29k – $63k per year (Estimated) • In office • 3+ years exp • Bengaluru
Python
Verilog
C++
SystemVerilog
Perl
SystemC
DevOps
Linux
Unix
Chips/EDA
UVM
Apply
Formal Verification 8 hours ago
≈ $34k – $74k per year (Estimated) • In office • 5+ years exp • Bachelor's Degree • Bengaluru
Python
Verilog
C++
SystemVerilog
VHDL
Perl
SystemC
Chips/EDA
UVM
Formal Verification
Synopsys VC Formal
Apply
See all jobs
This is one of many
745,032 more open roles from verified company boards, updated every day.