FPGA and RTL Design Engineer

Requirements:

• Experience Required: 4 to 10 years of relevant FPGA design/verification experience.
• Candidates with strong hands-on FPGA development and debugging experience will be preferred.
• Educational Qualification: B. E. /B. Tech. or M. E. /M. Tech. in Electronics, Electronics and Communication, Electrical Engineering, VLSI Design, Embedded Systems, or related disciplines. Candidates from reputed engineering colleges and universities will be preferred.
• FPGA Design Engineer Requirements: Digital Design Fundamentals.
• Strong understanding of combinational and sequential logic, finite state machines (FSM), clock domain crossing (CDC), and synchronization techniques.
• Timing Analysis and Timing Closure: Setup Time, Hold Time, Recovery/Removal Checks, Slack Analysis, and Timing Violation Debugging. HDL Development: Strong Verilog/SystemVerilog and/or VHDL coding skills in RTL design, simulation, synthesis, and FPGA implementation protocols.
• Knowledge: UART, SPI, I2C, Ethernet, and PCIe. Added advantage: JESD204B/JESD204C, 10G/25G/40G/100G Ethernet MAC, MACsec, IPsec, high-speed serial interfaces, DSP, and signal processing.
• Hands-on implementation of DSP algorithms in FPGA.
• Experience with filtering, FFT, digital signal processing pipelines, and optimization techniques is highly preferred for FPGA platforms.
• Practical experience with FPGA boards from Xilinx/AMD Microchip (Microsemi) and Intel (Altera).
• Debug and validation of FPGA bring-up and board-level debugging using ChipScope/ILA/SignalTap or equivalent debugging tools; hardware validation and troubleshooting.
• Experience using oscilloscopes, logic analyzers, and lab equipment and FPGA tools.
• Experience with any of the following tools: Vivado, Libero SoC, Quartus Prime, and ModelSim/QuestaSim.
• Experience with additional FPGA design tools will be an added advantage, including "RTL design for low-power implementations" and "Knowledge in Partial reconfiguration, " also in the list as an added advantage.