1,927,509open jobs
113,040companies
250,140added this week
Browse all
Salary
≈ $246k – $467k per year (Estimated)
Location
Hybrid (Mountain View, New York, United States)
Seniority
Staff
Visa
H-1B filings in 12 months: 1 · for this role: 1
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 22, 2026. First seen by Alion on Oct 21, 2026. Normal Computing scores A on the Alion truth index.

Overview
Company
Impact
Profile match
Normal Computing is an artificial intelligence and semiconductor technology company headquartered in New York City, New York, and founded in 2022. The firm develops a full-stack platform including AI-native Electronic Design Automation software and thermodynamic Application-Specific Integrated Circuits designed to optimize AI inference and long-context reasoning. Backed by investors such as Samsung Catalyst, the company partners with major semiconductor manufacturers to deploy its co-design solutions for complex system-on-chip verification and hardware acceleration.

Normal Computing | Build with Us

Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.

The Role

As a Lead RTL Design Engineer at Normal, you will lead and own the design of the digital logic at the heart of Normal's thermodynamic hardware. This work sits at the intersection of classical ASIC design, novel computing architectures, and a development environment where the hardware and the algorithms are built together, not in sequence.

You will lead and own RTL from microarchitecture to tapeout: writing microarchitecture specifications, creating synthesizable SystemVerilog, working with design verification engineers fully test the design using conventional and formal methods, and working closely with physical design to make sure the design meets area and timing constraints. As a Lead, you will help with hiring, create and refine the design methodology, organize the design team around schedule and track progress. Because Normal's chips are not standard accelerators, the Lead RTL engineer here is closer to first-principles decisions than at a larger company. You will be shaping architecture, not just implementing it.

This role requires a seasoned engineer with a track record of driving key initiatives, energizing the RTL team, and fostering cross-functional alignment across architecture, verification, and physical design. The ideal candidate has successfully led silicon through tapeout sign-off, played an active role in RTL implementation and design closure, and thrives in a dynamic setting where system specifications evolve alongside architectural and design development.

What You Will Own

  • Team Leadership: Organize and set the standard and high expectations for the RTL design team. Foster a collaborative and execution focused environment.

  • RTL Design: Create and enforce RTL coding standards. Write and own synthesizable RTL in SystemVerilog across blocks ranging from datapath logic to control and memory interfaces.

  • Microarchitecture: Work with architecture to translate high-level specifications into implementable microarchitectures.

  • Verification: Work closely with the verification team to review verification plans, assist on debug, and become a partner in closing coverage.

  • Physical Design Collaboration: Collaborate with physical design on timing closure, PPA optimization, floorplanning constraints, and DFT.

  • Design Reviews: Participate in design reviews and contribute to architecture decisions, not just implementation.

  • Tapeout & Bring-up: Support tapeout preparation, create tapeout criteria, signoff on tapeout readiness, and post-silicon bring-up as needed.

What Makes You a Great Fit

  • Experience leading an RTL design team through multiple tapeouts. This includes block and toplevel work.

  • Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route for multiple blocks and design.

  • Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront

  • Strong debugging instincts across simulation, waveforms, and formal counterexamples

  • Ability to work directly with architects and physical designers

Bonus Points

  • Experience at an AI chip company where design and verification were tightly coupled

  • Experience with multiple interface architectures, for example PCIe, Ethernet, and memory devices.

  • Familiarity with FPGAs

  • Experience with AI-assisted RTL or EDA tooling in your design workflow

  • Exposure to physical design constraints, floorplanning, or timing-driven RTL development

Equal Employment Opportunity Statement

Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.

Accessibility Accommodations

Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at [email protected].

Privacy Notice

By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Applicant Privacy Notice.

Free account
Stop reading job ads. Get the ones that fit.
One free account turns this page into a shortlist built around your stack, your level and your pay.
Match on every job. Stack, seniority, pay and location, scored against your profile.
1,927,509 open roles. Read straight off company career pages, refreshed every day.
Unlimited applications. Every one you send is tracked in one place, on-site or on a company board.
3 tailored CVs a month. Rewritten for the exact job you are applying to. Included free.
Create a free account Continue with Google
Free forever. No card. Under a minute.

Your match

How well do you fit this role?
Two answers are enough for a real match. No account needed.
Check my fit
Answers stay in this browser until you create an account.

Recommended for you based on this role

Hardware
Similar stack
Same company
Mountain View
≈ $135k – $256k per year (Estimated) • In office • Secret • 10+ years exp • Camden
Python
MATLAB
Chips/EDA
Mentor Xpedition
Apply
$137k – $185k per year • In office • TS/SCI • Full-Time • 20+ years exp • Bachelor's Degree • Albuquerque
Defense
MIL-STD-461
Apply
$201k – $314k per year • Equity • In office • Full-Time • 8+ years exp • Bachelor's Degree • El Segundo
Apply
$161k – $241k per year • In office • Top Secret • Full-Time • 11+ years exp • Bachelor's Degree • San Diego
Python
C++
VHDL
Apply
$180k – $200k per year • Equity • In office • 8+ years exp • PhD • San Jose
Python
C++
MATLAB
AI/ML
Claude Code
AI Agents
LLM
Apply
In office • Internship • Milan
Verilog
SystemVerilog
Chips/EDA
UVM
Apply
≈ $17k – $42k per year (Estimated) • In office • Full-Time • 5+ years exp • Master's Degree • Bengaluru • Hyderabad
Verilog
SystemVerilog
DevOps
Unix
Chips/EDA
Siemens QuestaSim
UVM
Apply
≈ $169k – $308k per year (Estimated) • In office • Bachelor's Degree • San Jose
SystemVerilog
Chips/EDA
Xilinx Vivado
Apply
≈ $168k – $319k per year (Estimated) • In office • Santa Clara
Python
Verilog
Ruby
SystemVerilog
Perl
Apply
FPGA Verification 1 day ago
In office • Full-Time • Bengaluru
Python
Verilog
SystemVerilog
VHDL
Chips/EDA
Intel Quartus Prime
Siemens QuestaSim
Siemens ModelSim
UVM
Xilinx Vivado
Synopsys ZeBu
Cadence Palladium
Synopsys HAPS
Cadence Protium
MedTech
Verification & Validation
Apply
$200k – $400k per year • Hybrid • Full-Time • 7+ years exp • London • New York • Mountain View
Python
DevOps
HPC
Chips/EDA
Synopsys PrimeTime
Synopsys IC Compiler II
Siemens Calibre
Cadence Pegasus
Apply
System Architect 1 day ago
$200k – $400k per year • Hybrid • Full-Time • New York • London • Mountain View
Apply
ASIC Architect 6 days ago
$200k – $400k per year • Hybrid • Full-Time • PhD • London • New York • Mountain View
Python
C++
SystemVerilog
AI/ML
Quantization
Diffusion Models
LLM
KV Cache
Apply
FPGA Platform Lead 9 days ago
$250k – $340k per year • Hybrid • Full-Time • New York • Mountain View
Python
C++
SystemVerilog
VHDL
DevOps
GitLab CI
CI/CD
Docker
Chips/EDA
UVM
Xilinx Vivado
Cocotb
Synopsys HAPS
Apply
Hardware Engineer, RTL 2 months ago
$200k – $400k per year • Hybrid • Full-Time • New York • London • Mountain View
SystemVerilog
Chips/EDA
CVA6
Apply
$150k – $207k per year • Equity • Hybrid • Master's Degree • Boston • Mountain View
Python
MATLAB
DevOps
HPC
Apply
≈ $99k – $193k per year (Estimated) • In office • 2+ years exp • Bachelor's Degree • Mountain View
Rust
C++
AI/ML
Gemini
Apply
≈ $64k – $123k per year (Estimated) • In office • 2+ years exp • Bachelor's Degree • Mountain View
Apply
≈ $127k – $284k per year (Estimated) • In office • 2+ years exp • Bachelor's Degree • Mountain View
Python
C++
AI/ML
Computer Vision
Management
Google Maps
Apply
≈ $183k – $317k per year (Estimated) • In office • 12+ years exp • Bachelor's Degree • Mountain View
Mobile
Material Design
Design
Figma
Apply
See all jobs
This is one of many
1,927,509 more open roles from verified company boards, updated every day.