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Salary
≈ $146k – $277k per year (Estimated)
Location
In office (San Jose)
Seniority
Architect
Visa
H-1B filings in 12 months: 104 · for this role: 73 · green card filings: 55

Confirmed on the employer's own hiring board on Oct 20, 2026. First seen by Alion on Oct 13, 2026. MediaTek scores A on the Alion truth index.

Overview
Company
Impact
Profile match
MediaTek Inc. is a global fabless semiconductor company specializing in system-on-chip (SoC) architectures and digital multimedia processing technologies. The enterprise designs and markets integrated circuits for smartphones, smart home devices, IoT hardware, wireless connectivity solutions, automotive electronics, and custom AI chips for edge and cloud applications. Headquartered in Hsinchu, Taiwan, the organization operates an international network of research, development, and sales offices serving original equipment manufacturers (OEMs) and technology brands worldwide.
About the team:

MediaTek’s Data Center team is at the forefront of innovation, driving the development of cutting-edge technologies that power the world's most advanced data centers. We are a dynamic group of system architects, packaging technology developers, and SoC design experts dedicated to creating high-performance, efficient, and reliable solutions. Our team collaborates closely to push the boundaries of technology, ensuring optimal performance, power efficiency, and scalability for data center applications. Join our Data Center team and be a part of the technological revolution that is shaping the future of data centers. If you are passionate about innovation and have the expertise to drive strategic technology development, we would love to hear from you.

Responsibilities:

Lead research and development of package architecture for AI accelerators and data center products.

Responsible for defining reference packaging architecture and methodology for high-power, high-bandwidth multi-chiplet systems, with emphasis on concept development, STCO modeling, and technology selection.

collaborative leader with a strong technical background in semiconductor packaging, metrology, and characterization, who will develop and maintain strong, strategic partnerships with internal engineering teams across packaging, reliability, test, technology integration, and product development, and build collaborative relationships with external partners to ensure alignment of technology and product roadmaps.

Provide technical leadership and maintain a deep understanding of industry trends and advancements in semiconductor packaging and characterization.

Lead architecture definition of advanced packaging solutions such as 2.5D/3D, CPO, IVR, and HSIO. Partner across silicon, SI/PI, thermal/mechanical, reliability, platform, and vendor teams.

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