ASIC Engineer, Emulation

Meta is hiring an ASIC Emulation Engineer within the Infrastructure Silicon organization. We are looking for individuals with deep expertise in pre-silicon emulation to build and validate IP and System on Chip (SoC) designs for data center applications. In this role, you will provide technical leadership in emulation methodology, infrastructure, and debug, working closely with Architecture, Design, Formal Verification, and Post-Silicon teams to enable first-pass silicon success. You will drive emulation strategy across complex ASIC programs, ensuring high-fidelity functional validation of Meta's custom silicon at scale.

Responsibilities

Provide technical leadership in emulation-based design verification methodology for custom ASIC and SoC designs targeting data center infrastructure Define and drive emulation strategy, including partitioning, compilation, bring-up, and debug flows for large-scale SoC designs Develop and maintain scalable emulation environments, including testbench infrastructure, transactors, and bus functional models for hardware-software co-verification Collaborate with architecture and RTL design teams to ensure emulation readiness and optimize designs for emulation platform constraints Lead emulation bring-up efforts, including root-cause analysis of compilation failures, runtime issues, and functional bugs across IP and SoC levels Define and track emulation coverage closure plans, coordinating with simulation and formal verification teams to achieve comprehensive pre-silicon sign-off Evaluate and recommend EDA emulation platforms and tools, driving adoption of best practices across the silicon engineering organization Partner with software and firmware teams to enable early software bring-up and hardware-software integration validation on emulation platforms Mentor other engineers in emulation methodology, debug techniques, and flow automation, and contribute to long-term emulation roadmap planning

Qualifications

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of experience in design verification with a focus on emulation-based verification of ASIC or SoC designs Experience with industry emulation platforms such as Palladium, Veloce, or ZeBu, including compilation, partitioning, and runtime debug Experience developing emulation testbench infrastructure including transactors, virtual models, and hardware-software co-verification environments Proficiency in hardware description languages such as SystemVerilog and experience with verification methodologies including UVM Experience with scripting languages such as Python, Perl, or Tcl for flow automation and emulation infrastructure development Experience enabling early firmware or operating system bring-up on emulation platforms for data center SoC programs Experience with emulation-based bring-up of complex compute blocks such as CPUs, GPUs, network processors, or custom AI accelerators Experience integrating emulation platforms into CI/CD-based regression and coverage closure flows Familiarity with low-power verification techniques and clock domain crossing validation in an emulation context