Hardware Engineer, AI Accelerator Module Design

We are seeking a senior AI Accelerator Module Design Engineer to serve as the technical owner for the electrical and PCB design of accelerator modules supporting Meta's custom silicon (MTIA) and third-party AI accelerators. This is a lead individual-contributor role: you will own module-level electrical architecture end to end from requirements definition and ASIC package-to-board co-design through schematic, stackup, power delivery, bring-up, and volume production across multiple concurrent programs and silicon generations.

You will define the design methodologies, reference architectures, and design-rule standards that other engineers and ODM partners build against; resolve the hardest cross-domain trade-offs between signal integrity, power integrity, thermal, mechanical, and cost; and influence ASIC and rack-level architecture decisions upstream of the module. You will operate with minimal direction in an ambiguous, fast-moving environment, and will mentor and raise the technical bar for PCB and module engineers across the team.

Responsibilities

Own the end-to-end electrical architecture and PCB design of AI accelerator modules for high-performance, high-power, high-efficiency custom silicon (MTIA) and third-party accelerators Define module requirements and specifications in partnership with ASIC, platform, rack, and systems architecture teams; translate system-level targets into implementable board-level design intent Lead ASIC package-to-board co-design, including breakout routing strategy, substrate and interposer interaction, and escape feasibility analysis for high pin-count, high-bandwidth devices Architect power delivery networks for extreme-current loads (multi-hundred-amp rails), owning DC-DC topology and architecture trade-offs (performance, transient response, efficiency, area, cost), decoupling strategy, and plane/stackup partitioning Drive high-speed interface design across PCIe Gen5/Gen6, CXL, UCIe, DDR5/LPDDR, HBM, NVLink/scale-up fabrics, and Ethernet up to 800G, including simulation-guided stackup and channel budgeting Set the technical direction for SI/PI methodology in partnership with Signal and Power Integrity teams; define correlation strategy between simulation and measured silicon Define and own module-level design reviews; set the quality bar for schematic, layout, and DFM/DFT readiness across internal designs and ODM-executed designs Lead board and silicon bring-up and own root-cause analysis of the most complex electrical, power, and interoperability failures; drive corrective design action to closure Drive ODM/JDM partners through full NPI-to-mass-production cycles, holding partners to Meta design standards and schedule Develop reusable reference designs, design-rule libraries, and design automation that scale across programs and generations; publish and champion designs through the Open Compute Project Evaluate and qualify leading-edge technologies with industry partners - HDI and advanced substrates, embedded components, novel materials, co-packaged and coherent optics - and build the business case for adoption Identify cross-organizational problems and lead XFN efforts to resolution without being asked; influence decisions outside your direct scope through technical credibility rather than authority Mentor and develop PCB/module design engineers; contribute to hiring, calibration of technical standards, and team-wide best practices

Qualifications

BS in Electrical Engineering, Computer Engineering, or a related technical discipline 10+ years of experience in electrical and PCB design for high-speed, high-power digital systems (servers, accelerators, networking, or HPC) Demonstrated experience as the lead engineer taking multiple complex custom board or module designs from concept through volume production Expert-level proficiency with EDA tools for schematic capture and PCB design (Cadence Allegro/OrCAD, Altium Designer, or equivalent) Deep expertise in high-speed digital interface design (PCIe, CXL, DDR4/DDR5, HBM, Ethernet 25G-800G) and SerDes-based channel design, including stackup and channel budgeting trade-offs Deep expertise in power delivery network architecture for high-current loads, including DC-DC topology selection, transient and efficiency analysis, and plane/decoupling strategy Experience with ASIC or GPU package-to-board co-design and breakout routing for high pin-count devices Experience leading board and silicon bring-up, debug, and failure analysis using oscilloscopes, VNAs, TDR, and power analyzers Experience owning technical direction across multiple concurrent programs and influencing decisions across hardware, firmware, mechanical, thermal, and manufacturing organizations Experience driving external ODM/JDM or component partners through design and production cycles Experience communicating technical trade-offs and recommendations in writing and verbally to engineering leadership MS or PhD in Electrical Engineering with emphasis on electromagnetics, signal integrity, or power electronics Track record of establishing design standards or methodologies adopted at organizational scale Experience defining design automation and verification flows (Python, SKILL/LISP, or equivalent) adopted beyond their own program Experience designing accelerator modules for custom in-house silicon, including involvement in silicon requirements definition Experience with next-generation interconnect: PCIe Gen6/Gen7, CXL 3.x, UCIe, scale-up fabrics, or co-packaged/coherent optics Experience with HDI, rigid-flex, embedded component, and advanced substrate technologies, including vendor capability development Hands-on expertise with SI/PI simulation and correlation tools (Ansys HFSS, Cadence Sigrity, Keysight ADS/PathWave, or equivalent) Contributions to open-source hardware or the Open Compute Project, or external technical publications and standards-body participation 15+ years of experience in module or board design for AI/ML accelerators, data center, or HPC hardware Experience with liquid-cooled and thermally-constrained module design, including thermal-aware placement and stackup techniques