Machine Learning SoC Architect

In this role, you will own ASIC architecture specification, establish the performance modeling methodology and long-term silicon roadmap strategy, partnering with other silicon, and software teams to ensure Meta's infrastructure silicon meets the demanding throughput, latency, and efficiency targets required at hyperscale.

Responsibilities

Work on algorithm analysis, performance analysis and architecture definition of Machine Learning ASICs Map Data Center workloads to heterogeneous ASICs that contain multiple different programmable processors and hardware accelerators. Perform detailed calculations to specify computation throughput, memory bandwidth and latency; evaluate performance v/s area v/s power tradeoffs Drive the architecture definition of one or more of the following ASIC sub-systems: compute, memory, Network-On-Chip (NoC), collectives, debug etc. and chiplet based multi-die SoCs Identify appropriate workloads and micro-benchmarks to be used for performance analysis and drive this analysis on simulation and emulation platforms to define and validate the architecture Evangelize your innovative architectural solutions with your peers and leadership, while mentoring members of the architecture team Collaborate with cross functional teams working on RTL design, Design Verification, Firmware/Software development, Pre-Post silicon validation and Program Management to deliver first pass functional silicon on an aggressive schedule Collaborate with software and firmware teams to ensure that the ASIC meets end to end application performance goals while maintaining ease and efficiency of software development

Qualifications

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience Experience and knowledge of Computer Architecture concepts such as microprocessor architecture, memory systems, on-chip interconnection networks, hardware/software partitioning etc 12+ years of prior experience in defining and delivering multiple high performance ASICs into production, with focus on architecture definition and performance analysis Experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom silicon or SoC designs Proficiency in C++ and Python for developing simulation models, automation frameworks, and performance analysis tools Experience with performance analysis of data center, AI accelerator, or high-performance computing workloads on custom silicon Experience defining architecture and microarchitectural specifications and driving cross-functional alignment across architecture, RTL, and physical design teams Familiarity with post-silicon performance validation and model-to-hardware correlation methodologies Programming in C or C++ with knowledge of mapping hardware algorithms to efficient C/C++ code Master's or PhD degree in Electrical Engineering, Computer Engineering or related field Domain knowledge in one or more of power/performance tradeoffs, ML networks, ML frameworks such as Pytorch Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs