Semiconductor Yield / Defect Engineer (Wafer Fab, SEM Defect Review)

Role Title: Semiconductor Yield / Defect Engineer (Wafer Fab, SEM Defect Review)

micro1 is engaging Semiconductor Yield / Defect Engineers (Wafer Fab, SEM Defect Review) to support a customer engagement focused on advancing semiconductor manufacturing analytics. In this role, you'll apply your expertise to help train next-generation AI systems. Your work will shape how models learn, reason, and perform through high-quality, real-world input. No prior experience in AI is required — your domain knowledge is what matters. This opportunity is ideal for yield, defect, or process integration experts with direct hands-on experience in wafer fab production environments, especially those familiar with facilities operating their own sort floors. Retired or former fab engineers are highly encouraged to participate and share their invaluable experience.

1. Conduct SEM (Scanning Electron Microscope) defect review and accurate classification of defects observed in wafer fabrication processes.
2. Interpret and analyze yield loss mechanisms, correlating defect patterns with process-related issues.
3. Evaluate excursion events and make informed lot-hold or release recommendations based on empirical evidence and industry best practices.
4. Review, interpret, and annotate wafer sort and test floor data, including bin maps and parametric datasets.
5. Identify defect paretos and contribute to source attribution analysis to trace root causes.
6. Document observations, communicate technical findings, and provide actionable feedback in clear, concise written and verbal formats for integration into AI learning modules.

1. Extensive hands-on experience in wafer fab environments, with a focus on SEM-based defect review and yield analysis.
2. Demonstrated expertise in production fabs with integrated sort/test floors; experience limited to research cleanrooms does not qualify.
3. Proficiency with defect classification methodologies, excursion management, and yield improvement strategies.
4. Strong ability to analyze wafer sort/bin data and interpret test floor metrics to inform defect and yield investigations.
5. Exceptional written and verbal communication skills, able to explain complex technical concepts to diverse audiences.
6. Background in process integration or defect/yield engineering at major semiconductor manufacturing facilities.
7. Experience as a retired or former fab engineer considered a valuable asset.

Originally posted on Himalayas