Principal Engineer-Design (SoC Integration and RTL/IP)

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Job Description:

Job Summary

The dsPIC microcontroller group is seeking an experienced SoC Integration, RTL/IP Design, and FPGA Engineer to lead SoC integration, RTL development, IP design, and FPGA prototyping activities. The candidate will work closely with architecture, verification, and physical design teams to deliver high-quality hardware solutions.

Key Responsibilities

SoC Integration

• Perform top-level and subsystem integration of processors, memories, peripherals, and custom IPs.
• Integrate IPs using proprietary bus interfaces and AMBA AXI, AHB / APB protocols.
• Handle clock/reset integration, interrupt routing, address mapping, and pad / pin connectivity.
• Resolve chip-level Lint / Synthesis / Timing issues perform CDC / RDC analysis and implement relevant fixesOwnership of post-silicon debug and ECO revisions of the chip

RTL and IP Design

• Develop synthesizable RTL using SystemVerilog.
• Design reusable peripherals, controllers (for memories, ADCs, PWMs), wrappers, and power management modules.
• Resolve Lint / Synthesis / Timing issues; resolve CDC / RDC errors
• Perform RTL reviews, synthesis support, timing optimization, and design debug.
• Maintenance, enhancements and management of older IP

Technical Leadership

• Collaborate with architecture, verification, DFT, physical design, firmware, and system teams.
• Lead design reviews, mentor junior engineers, and drive technical improvements
• Help with key decisions related to IP and product definition and implementation

Requirements/Qualifications:

Required Skills

• Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, or a related field with 10+ years of experience in ASIC/SoC design, RTL development, FPGA, or SoC integration.
• Strong knowledge of SystemVerilog and AMBA AXI/AHB/APB protocols.
• Experience with SoC integration, IP development, clock/reset architecture, and memory mapping.
• Hands-on experience with Vivado or Quartus, synthesis, STA, and timing closure.
• Familiarity with simulation tools such as QuestaSim, VCS, or Xcelium.
• Knowledge of CDC/RDC, RTL lint, and Python/Tcl scripting.

Preferred Qualifications

• Experience with ARM/RISC-V-based SoCs, Ethernet, USB, SPI, I2C, and UART interfaces.
• Knowledge of low-power design, DFT integration, and Formal-based verification.
• Experience with FPGA synthesis, place and route, timing closure, constraint development and FPGA-based validation.
• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.

Expected Deliverables

• Integrated SoC/subsystem RTL and reusable IP modules.
• FPGA implementation and validation results.
• Design quality reports and integration documentation.

Role Expectation: Independently drive SoC integration, IP design, and FPGA prototyping while providing technical leadership and ensuring robust, reusable hardware designs.

Travel Time:

Physical Attributes:

Physical Requirements:

Microchip Technology Incis an equal opportunity/affirmativeaction employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.

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