Hardware Verification Engineer - Microsoft Azure
Confirmed on the employer's own hiring board on Oct 14, 2026. First seen by Alion on Oct 12, 2026. Microsoft scores B on the Alion truth index.
Microsoft is building the fastest and most reliable networks for AI and cloud data centers. Microsoft Azure is one of the largest public cloud platforms worldwide, providing a great channel for product impact that touches the lives of millions of users daily. Microsoft’s partnership with world leaders in AI technology provides unparalleled opportunities for innovation at the cutting edge of high-performance computing and networking.
Our team has delivered Azure Boost to production through 2 generations and we are now looking for talented hardware design engineers to join our team, developing Azure’s next generation networking devices.
Microsoft’s innovative approach for hardware/software co-design leverages custom-designed hardware to offload and accelerate many types of computations and functions of the Azure network. Our vertical work environment offers an unparalleled opportunity to define end-to-end features, implement & test them, participate in their deployment in the cloud, and see your work used on a global scale!
Come join us and be challenged daily as you build advanced hardware/software acceleration solutions for some of the world’s largest datacenter networks and AI supercomputers. This is a great opportunity to join a team that has built some of the largest scale cloud systems ever deployed and learn from the very best.
Responsibilities
Design verification environments for units and full devices, based on deep understanding of customer requirements, DUT functionality, and system architecture.
Design and implement VIP, constrained-random testbenches, assertions, coverage, and verification infrastructure using SystemVerilog/UVM.
Develop and execute test/coverage plans to verify hardware designs and reach cloud-grade quality.
Work closely with architects, RTL designers, firmware/software engineers, and validation teams throughout the design and verification lifecycle
Debug complex design and verification failures, perform root-cause analysis, and collaborate with design and architecture teams to drive issues to closure.
Qualifications
At least 4 years of proven experience in verification of large ASIC/FPGA designs
BSc/MSc in Electrical Engineering, Computer Science, or Computer Engineering, from a major university.
Other
Proven knowledge of hardware verification concepts and tools (UVM, unit level and full chip verification, coverage-based verification)
A versatile can-do, problem-solving attitude, and desire to handle a wide array of challenges.
Proven communication skills in English.
- Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:
- Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.