Design Verification Engineer

Role : Design Verification Engineer SerDes / SoC

Experience : 4-5 years

Notice Period : Within 45 Days

Positions : 1

Budget : max 4X ( 16 20 LPA )

Location : Bangalore

Domain : Semiconductor / VLSI Design Services

Key Requirements :

Expertise in SystemVerilog and UVM :

- Strong hands-on experience with SystemVerilog and Universal Verification Methodology (UVM) for developing robust, reusable, and scalable verification environments. The candidate should be comfortable working with UVM components such as agents, drivers, monitors, sequencers, scoreboards, reference models, and coverage collectors, and should be able to build verification infrastructure from the ground up or enhance existing environments.

Experience in high-speed SerDes/SoC/IP verification :

- Experience in verifying high-speed SerDes interfaces, SoCs, or semiconductor IPs, with a strong understanding of digital verification methodologies. The candidate should have exposure to verifying complex IP blocks and subsystems, including functional behavior, interface interactions, data integrity, and protocol-level functionality in high-speed designs.

Proficient in testbench architecture, constrained-random verification, and regression/coverage closure :

- Strong understanding of verification testbench architecture and the ability to design modular and reusable UVM-based environments. Experience developing constrained-random test scenarios, creating functional and protocol-oriented test cases, managing regressions, analyzing failures, and driving functional/code coverage closure is required. The candidate should be able to identify coverage gaps and develop additional scenarios to achieve verification completeness.

Debugging skills using Verdi/SimVision :

- Strong simulation-debugging capabilities using industry-standard tools such as Verdi and/or SimVision. The candidate should be able to analyze waveforms, trace signal behavior, identify root causes of functional failures, debug testbench issues, and work closely with design teams to resolve simulation and integration problems efficiently.

Familiarity with CDC/Formal/AMS/Gate-level simulation is a plus :

- Exposure to additional verification methodologies such as Clock Domain Crossing (CDC), Formal Verification, Analog/Mixed-Signal (AMS) verification, and Gate-Level Simulation (GLS) will be considered an advantage. Candidates with experience working across multiple stages of the verification lifecycle and collaborating with different verification disciplines will be preferred.

Key Responsibilities :

Develop/maintain UVM environments for SerDes IPs/subsystems :

- Design, develop, enhance, and maintain UVM-based verification environments for SerDes IPs and related subsystems. This includes developing reusable verification components, integrating protocol/interface models, maintaining existing testbenches, and ensuring that the environment can effectively support functional and protocol-level verification.

Create test cases for link training, power modes, and protocol compliance :

- Develop comprehensive test scenarios covering critical SerDes functionality, including link initialization and training, different power-management modes, error conditions, state transitions, and protocol compliance. The candidate will be responsible for creating both directed and constrained-random tests to validate expected behavior across different operating conditions and corner cases.

Drive coverage closure and debug simulation/integration issues :

- Analyze functional and code coverage results, identify coverage holes, develop additional tests where required, and drive the verification effort toward coverage closure. The role also involves debugging simulation failures, testbench issues, integration problems, protocol violations, and unexpected DUT behavior, followed by root-cause analysis and coordination with the Design and Architecture teams for resolution.

Collaborate with Design/Architecture teams :

- Work closely with Design, Architecture, RTL, Integration, and other Verification teams to understand specifications, clarify design intent, review verification requirements, identify potential corner cases, and resolve issues. The candidate will contribute to verification planning and ensure that verification activities remain aligned with the overall IP/SoC development objectives.

Preferred :

Experience with PCIe, Ethernet, USB, CXL, or MIPI :

- Prior verification experience with one or more high-speed industry protocols such as PCIe, Ethernet, USB, CXL, or MIPI will be highly preferred. Candidates should ideally have an understanding of protocol behavior, transaction flows, link states, compliance requirements, and relevant verification scenarios associated with these interfaces.

Familiarity with PHY integration or protocol VIP :

- Experience working with PHY integration, protocol verification IP (VIP), or interface-level verification will be an advantage. Familiarity with integrating and configuring protocol VIPs, generating protocol transactions, monitoring interface behavior, and validating interactions between the PHY, controller, and surrounding SoC/IP components will be beneficial.

Skills

Design Verification, SERDES, SoC, System Verilog, UVM, Verification, PCI-e, Physical Verification