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Nokia is a Finnish telecommunications equipment company founded in 1865 as a paper mill, which became the world's largest mobile phone maker in the 1990s before selling that business to Microsoft in 2014. It now supplies network infrastructure to operators and enterprises, covering radio access equipment for mobile networks, optical and IP routing for transport networks, fixed broadband access, and a technologies division that licenses its cellular patent portfolio. Headquartered in Espoo and listed in Helsinki and New York, it runs Nokia Bell Labs as its research arm and has been expanding into data centre networking as operator spending has slowed.

As part of Nokia’s Silicon Photonics Supply Chain team, you will be responsible for managing and reviewing the wafer level testing that supports high volume production of our next generation Silicon Photonic transceivers. You will review in-line metrology and electrical test data from the Fab and connect it to our silicon photonic wafer acceptance test (WAT) and known-good die test (KGD) data to help drive improvements in yield, and review SPC charts to detect trends. You will oversee a fleet of test equipment and work with engineers and operators at our Fab and OSAT partners to ensure that we are generating the highest quality data, and you will work with our Test Engineering teams to drive improvements to our test throughput.

  • Reviewing and correlating data from multiple sources to drive yield improvements
  • Overseeing and optimizing utilization of a fleet of wafer-scale optical test equipment
  • Capacity planning for wafer test equipment
  • Organizing and convening the material review board
  • Planning for and coordinating the implementation of software and hardware upgrades
  • Being the technical interface between Nokia R&D and external test Supplier
  • Responsible for change implementation at external test supplier.

You have:

  • Advanced Degree in Engineering, Physics, Statistics, or related field
  • 3-5 years of yield or metrology engineering experience in a leading-edge semiconductor fab
  • Strong proficiency in wafer scale yield analysis: experience creating and reviewing Pareto charts, and analyzing wafer maps to look for spatial patterns
  • Experience working with defect inspection tools and interpreting their data
  • Experience working with change control systems and PLM tools
  • Solid interpersonal, communication and problem-solving skills in order to interact with engineering staff, external vendors and contractors effectively.

It will also be good if you have:

  • Experience managing a fleet of metrology equipment
  • Proficiency in Python, and exposure to numerical and statistical packages
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