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Salary
≈ $14k – $34k per year (Estimated)
Location
In office (Bengaluru)
Seniority
Junior · 2+ years exp
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 8, 2026. First seen by Alion on Oct 8, 2026. NVIDIA scores A on the Alion truth index.

Overview
Company
Impact
Profile match
NVIDIA is an American technology company founded in 1993 that invented the graphics processing unit and has become the dominant supplier of accelerated computing platforms for artificial intelligence. Its portfolio spans data centre GPUs and systems built on the Hopper and Blackwell architectures, GeForce consumer graphics, automotive and robotics platforms, high-speed networking acquired with Mellanox, and the CUDA software stack that binds the ecosystem together. Headquartered in Santa Clara, California, the company sells to cloud providers, enterprises, research institutions and gamers worldwide and is one of the most valuable listed businesses on the Nasdaq.

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. Make the choice to join us today. NVIDIA is an equal opportunity employer. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. We are looking for a DFT Engineer.

What you'll be doing:

  • As a member in our team, you will be responsible for end-to-end DFT from RTL design to Gate level scan insertion to Verification (including JTAG, boundary scan, security mechanisms, and test clocking-across various test modes, including multiple ATPG configurations) to silicon bring-up.

  • Your responsibility will also include verification and silicon bringup of Scan ATPG and other DFT features.

  • In addition, you will help develop and deploy DFT methodologies for our next generation products.

  • Be apart of innovation to strive improve the quality of DFT methods.

  • You will also need to work with multi-functional teams to incorporate DFT features into the chip.

  • Occasional travel and also some late hours online meetings involved during critical milestones.

What we need to see:

  • BSEE or MSEE from reputed institutions or equivalent experience with 2+ years of experience

  • You should be well versed with static timing Analysis, ECO, ASIC/Logic Design Flow, HDL and Digital logic design.

  • Experience in RTL and Gates verification and simulation.

  • You need to be familiar with BIST architecture and JTAG/IEEE1149.1/IEEE1500.

  • Strong DFT knowledge in Scan ATPG, compression techniques and memory test.

  • Strong analytical and problem solving skills with good scripting knowledge (either Perl / Python)

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