Senior SoC Performance Verification Manager

We are looking for a SoC Performance Verification Manager to join NVIDIA's Networking Chip Design team! In this hands-on role, you will provide technical leadership and manage the SoC performance verification group across NVIDIA's next-generation DPUs and SmartNICs. You will own end-to-end pre-silicon performance signoff for the SoC. We are looking for someone who thrives on building high-performing teams, driving execution across multiple parallel projects, and partnering with architecture, microarchitecture, IP, SoC integration, and program management teams to deliver world-class silicon.

What You'll Be Doing:

• Lead, mentor, and grow a team of verification engineers. Define team structure, hiring plans, and career development paths to build a strong, scalable organization.
• Provide technical leadership in defining and executing the performance verification strategy for sophisticated NIC designs, partnering closely with design, architecture, and modeling teams to identify, analyze, and mitigate performance bottlenecks across the design pipeline.
• Architect and implement reusable testbench infrastructure components and develop targeted test scenarios for full-chip NIC performance verification, drawing on a deep understanding of NIC microarchitecture and traffic flows. Build infrastructure and tooling for efficient performance debugging.
• Develop detailed performance test plans to verify next-generation features.
• Use advanced verification methodologies and tools, including Specman/e and SystemVerilog/UVM.
• Establish and improve design and verification methodologies and best practices. Enable AI workflows to increase team productivity and improve design quality across tape-outs.

What We Need to See:

• A B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering, or equivalent experience.
• 10+ overall years of experience in ASIC/SoC verification, including 3+ years in a people management or technical leadership role overseeing teams of multiple engineers.
• A strong understanding of verification methodologies, including UVM, constrained-random verification, and coverage-driven verification techniques.
• A strong understanding of digital design fundamentals, including RTL coding in Verilog/SystemVerilog, architecture, microarchitecture, and power analysis.
• Demonstrated ability to manage SoC teams while balancing resources, schedules, and quality trade-offs.
• Experience with EDA tools for simulation and debugging.
• The ability to communicate technical status, risks, and trade-offs clearly to engineering leadership and cross-functional partners.

Ways to Stand Out from the Crowd:

• Multiple years of experience verifying the performance of complex designs.
• Experience or a background in networking-related domains.
• Hands-on experience developing fully agentic workflows to improve team processes.
• Experience building or scaling verification infrastructure, including regression frameworks, coverage automation, or CI/CD pipelines for hardware.

Skills

ASIC, SOC, UVM, Verification