Signal and Power Integrity Engineer
Confirmed on the employer's own hiring board on Oct 18, 2026. First seen by Alion on May 13, 2026. NVIDIA scores B on the Alion truth index.
We are now looking for Signal & Power Integrity Engineer. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. This is a dynamic team working with state of the art, unique technology. If you are someone that loves a challenge, come join this diverse team and help move the needle!
What you'll be doing:
Drive board/system level signal and power integrity requirements
Lead board/system SI/PI design activities, including PCB stackup/material selection, design guide implementation, layout review, and post-layout analysis
Work closely with Architecture, ASIC, Mixed Signal, Package, and PCB Design teams to design and ensure system SI/PI performance meets expectation before Gerber out, also work closely with Design Validation teams to support SI/PI failure analysis
Develop novel algorithms & new methodologies to improve SI/PI modeling efforts
Work with Application Engineering teams to support customers w/ SI/PI questions
VNA & TDR measurements to support model correlation efforts and improve confidence in design stage
What we need to see:
MS/BS in EE or equivalent experience
Minimum 1+ years of experience as a SI/PI engineer
Deep understanding of electromagnetic, specifically electromagnetic waves including transmission line theory and via properties
Proficient with HFSS, Sigrity, Hspice, and/or other simulation tools
Experienced with Cadence Allegro PCB designer and Constraints Manager
Understanding of high volume manufacturing variations and impact to channel signal integrity
Exposure to lab measurements including VNA & TDR experience
Passionate about SI/PI work
Good written & verbal interpersonal skills in English
Ways to stand out from the crowd:
Familiarity with NRZ/PAM-4 signaling schemes
Exposure to interface timing budgets and system modeling
Familiarity with high-speed I/O design concepts including clock generation, transmitter & receiver design, and equalization schemes
PDN analyses including model generation and time domain simulation
Experience w/ Matlab, Python, and C as well as exposure to package design