Verification Engineer - ARM Fabric Unit Level

We are seeking hardworking, determined, and imaginative individuals to join our automotive verification group. As the owner of HSIO IP's unit level verification, you will contribute to projects crafting the future of automotive chips and systems. You will gain direct experience of chip working with high-performance CPU and memory sub-systems, NOC-based interconnect fabric, high-speed I/Os, and various advanced technologies used in our Tegra chips.

What you'll be doing:

• You will develop UVM-based verification test benches and methodologies.
• These will verify our in house ARM architecture based distributed fabric needed to transport control, sidebands and data as needed.
• During the course of a project, you will drive the following aspects of verification for your unit:
• Architect the testbenches and craft verification environment using SV and UVM methodology
• Define test plans, tests and verification infrastructure for modules, clusters and systems
• Build efficient and reusable bus functional models, monitors, checkers, and scoreboards
• Implement functional coverage and coordinate the verification closure process for the unit
• Work with architects, designers, FPGA, and post-silicon teams to ensure that your unit is robust

What we need to see:

• BTech or MTech in ECE, EE, CSE, or an equivalent degree is required. Candidates should have 2+ years of demonstrated ability in verification closure of complex units, sub-systems, or SOC level verification.
• Proven experience in ARM architecture and protocols (AXI, AHB and APB)
• Experience in the latest verification methodologies like SV and UVM
• Good debugging and analytical skills with exposure to industry-standard verification tools for simulation and debug
• Good interpersonal skills, ability to work as a diligent teammate, and excellent communication skills to collaborate with cross-cultural global teams and work in a matrix organization

Ways to stand out from the crowd:

• Exposure on using AI (like Claude or Cursor) extensively for code development would be a big plus
• A mentality towards constant improvement and looking to build a multiplier effect through your work and automation
• Exposure to Formal verification would be excellent

Skills

ARM, SV, SystemVerilog, UVM