Lead digital verification engineer

Job Responsibility:

·Responsible for the pre-silicon verification ofnon-volatile memory controller modules.

·Responsible for defining digital verification strategy and plan for IP modules.

·Interface to Digital design teams to understand functionality and application of the IP subsystem, SoC system.

·Responsible for executing verification plan according to the product specification and verification requirements defined.

·Responsible for developing, debugging and running System Verilog UVM based verification environment for RTL/netlist simulation.

·Define and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level), run regression, collect and analyze code/functional coverage.

Job Qualification:

·Bachelor’s degree or above in Microelectronics, Electronics, Electrical Engineering, Computer Science or relevant disciplines, with 8+ years of experience.

·Understanding of SoC architecture and functionality

·Understanding of directed and constrained random verification methodology

·Good knowledge in UVM, Verilog, System Verilog, Shell

·Good software programming skills

·Good knowledge in Scripting like Perl, TCL or Python is a plus

·Understanding of AI-Powered developer assistance tools

·Good communication skills to interact with teams across the globe and work independently

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