1,097,669open jobs
63,892companies
187,136added this week
Browse all
Location
In office (Seoul)
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 2, 2026. First seen by Alion on Oct 2, 2026. NXP Semiconductors scores B on the Alion truth index.

Overview
Company
Impact
Profile match
NXP Semiconductors is a Dutch chipmaker established in 2006 when Philips spun out its semiconductor division, and it concentrates on embedded processing rather than general purpose computing. Its largest market is automotive, where it supplies radar sensors, vehicle networking, battery management and the secure processors behind keyless entry and digital car keys, alongside industrial and internet of things microcontrollers, mobile secure elements and communications infrastructure silicon. Headquartered in Eindhoven and listed on Nasdaq, it is one of the leading suppliers of near field communication and automotive processing chips in the world.

About the Team

NXP Semiconductors is seeking an Analog IC Layout Engineer to join the Central Layout Group serving the Power & Energy Business Line, with a primary focus on Automotive Power Solutions (APS).

The Central Layout Group delivers physical implementation expertise for complex mixed-signal and power management integrated circuits supporting multiple product lines worldwide. The team collaborates with Design, Verification, Package, Test and Product Engineering organizations across a global R&D network to develop next-generation automotive and industrial semiconductor solutions.

Role Summary

The successful candidate will contribute to the development of analog and mixed-signal integrated circuits, supporting physical implementation activities from block-level development through product integration. The role offers the opportunity to work within an international and multidisciplinary engineering environment.

Key Responsibilities

Layout Development

  • Develop Analog and Mixed-Signal layout blocks from schematic to tape-out
  • Support floorplanning and physical implementation activities
  • Optimize layouts for performance, matching, reliability and manufacturability
  • Contribute to top-level integration activities

Verification and Quality

  • Execute DRC, LVS, ERC and physical verification activities
  • Support parasitic extraction and post-layout analysis
  • Participate in design reviews and sign-off activities
  • Ensure high-quality layout deliveries following NXP methodologies

Cross-Functional Collaboration

  • Collaborate closely with Analog Design, Verification, Package, Test and Product Engineering teams
  • Support troubleshooting and problem-solving activities during product development
  • Contribute to continuous improvement of layout methodologies and best practices

Required Skills

  • Bachelor or Master Degree in Electrical Engineering, Electronics, Physics or Microelectronics
  • Knowledge of Analog IC Layout methodologies
  • Experience with Cadence Virtuoso Layout environment
  • Understanding of DRC/LVS verification concepts
  • Familiarity with Linux working environments
  • Strong analytical and problem-solving skills
  • Ability to collaborate effectively in multicultural and international teams
  • Fluent written and spoken English

Preferred Qualifications

  • Experience with Calibre, PVS or equivalent verification tools
  • Knowledge of CMOS, BCD or High Voltage technologies
  • Knowledge of Analog Mixed-Signal integrated circuits
  • Basic scripting skills (SKILL, Python, TCL or Shell)
  • Experience in automotive semiconductor development
  • Interest in layout automation and methodology improvements

More information about NXP in Korea...

#LI-29ec
Free account
Stop reading job ads. Get the ones that fit.
One free account turns this page into a shortlist built around your stack, your level and your pay.
Match on every job. Stack, seniority, pay and location, scored against your profile.
1,097,669 open roles. Read straight off company career pages, refreshed every day.
Unlimited applications. Every one you send is tracked in one place, on-site or on a company board.
3 tailored CVs a month. Rewritten for the exact job you are applying to. Included free.
Create a free account Continue with Google
Free forever. No card. Under a minute.

Your match

How well do you fit this role?
Two answers are enough for a real match. No account needed.
Check my fit
Answers stay in this browser until you create an account.

Recommended for you based on this role

Hardware
Similar stack
Same company
Seoul
In office • Full-Time • Seongnam
Chips/EDA
Synopsys HSPICE
Apply
≈ $47k – $109k per year (Estimated) • In office • Full-Time • 3+ years exp • Seongnam
Verilog
SystemVerilog
Apply
≈ $23k – $54k per year (Estimated) • In office • Full-Time • 3+ years exp • Dongguan
Apply
≈ $30k – $86k per year (Estimated) • In office • Full-Time • Shanghai
C++
Apply
≈ $28k – $65k per year (Estimated) • In office • Full-Time • 5+ years exp • Chengdu
Apply
$51k – $84k per year • In office • Full-Time • Mannheim
DevOps
Linux
Apply
≈ $16k – $42k per year (Estimated) • In office • Pune
SQL
Databases
Oracle
AI/ML
Anomaly Detection
DevOps
Splunk
Zabbix
Kibana
Datadog
Dynatrace
AppDynamics
AIOps
Incident Management
SLI/SLO/SLA
Linux
Unix
Management
ITIL
Apply
≈ $13k – $30k per year (Estimated) • In office • Pune
Python
SQL
DevOps
Linux
Unix
QA
Selenium
Apply
≈ $41k – $91k per year (Estimated) • Hybrid • Poznań
Python
SQL
Databases
PostgreSQL
DevOps
Rest API
Git
Docker
Linux
Management
Agile
Scrum
Apply
≈ $87k – $175k per year (Estimated) • In office • 10+ years exp • Bachelor's Degree • Mississauga
DevOps
Linux
Unix
Management
Jira
Apply
≈ $23k – $55k per year (Estimated) • In office • Full-Time • Noida
Apply
≈ $106k – $243k per year (Estimated) • In office • Full-Time • Austin
Management
Outlook
Apply
≈ $86k – $205k per year (Estimated) • In office • Full-Time • Master's Degree • Nijmegen
Chips/EDA
Cadence Virtuoso
Apply
$57k – $78k per year • In office • Full-Time • 5+ years exp • Master's Degree • Catania
Python
Verilog
SystemVerilog
Perl
Chips/EDA
Synopsys Design Compiler
Synopsys PrimeTime
Siemens QuestaSim
Formal Verification
Cadence Genus
Synopsys Formality
Apply
≈ $26k – $62k per year (Estimated) • In office • Full-Time • 10+ years exp • Bachelor's Degree • Pune
Verilog
SystemVerilog
Apply
≈ $34k – $81k per year (Estimated) • In office • Full-Time • Bachelor's Degree • Seoul
Apply
In office • Full-Time • 1+ year exp • Seoul
SQL
C#
C#
.NET
Databases
MS SQL
Apply
≈ $36k – $98k per year (Estimated) • In office • Seoul
Mobile
Material Design
Apply
≈ $93k – $204k per year (Estimated) • In office • Full-Time • 5+ years exp • Seoul
Apply
In office • Full-Time • 2+ years exp • Bachelor's Degree • Seoul
DevOps
AWS
Apply
See all jobs
This is one of many
1,097,669 more open roles from verified company boards, updated every day.