Senior Lead Engineer - STA
The Digital Physical Design Engineer is responsible for complete STA signoff for the SOC or Subsystem.
The individual is responsible for writing timing constraints, interacting with the counterpart functions, such as Frontend, DFT and IP to write correct constraints, refining constraints throughout SOC design cycle and constraints validation.
The individual must have exposure of AI and use AI in STA activities.
The individual is responsible for complete timing signoff till the tapeout for subsystem or full chip.
Must have leading capabilities on signoff function.
Must have worked on SDF generation and validation.
Must have all knowledge of SI closure.
Must have exposure to higher tech nodes such as 16nm and 5nm.
Must be conversant with physical design flows and functions and must possess good knowledge of placement, CTS and Routing.
The individual contributes to problem solving related to physical design. Contributes to define best Physical design strategy per technology node.
#LI-2734