Senior Lab Engineer - To support new capability PCT ( Power Cycling Test) Test in Seremban Rel lab

Job Summary:

An exciting opportunity to join the Global Reliability Labs . As a Reliability Engineer, you will have the opportunity to apply AQG324 Power Cycle stress strategies as well as support additional reliability stress operations. of other reliability stress tests and reliability standards. You will be working in a multi-cultural, cross functional engineering team performing reliability evaluation of new drivetrain power module products for introduction into the electric vehicle automotive market and other product markets.

Performance Objectives:

• To efficiently deliver high-quality stress data to enable effective decision making and risk assessments for technology development, product qualification, and production support.
• To execute flawlessly on the hardware design development & deliver to committed cycle-time
• To provide engineering support to setup of specific Reliability test and train lab personnel accordingly.
• To work closely with BU, Rel Eng including Lab Operations on new products Rel hardware and Reliability Stress events setup with proper buyoff done with appropriate documentation & Knowledge transfer and training done.
• Gain a full understanding of the automotive reliability specifications and guidelines including AQG324 and other Reliability standards
• Be able to configure, assemble, and debug power cycle test systems for lifetime assessment.
• Be able to configure, assemble, and debug fluid delivery systems for cooling power modules.
• Become proficient in running Seremban lab Reliability activities such as PCT, HTRB, HTGB, PTC and more.
• Be safety minded about power and other lab hazards.

• Reliability Lab Engineering work for IGBT, HV Si, HV SiC Discrete, IC and Module products.
• Design of hardware (such as Reliability Boards, Gate Driver IC Boards, DUT cards) for reliability testing and understanding of electronic circuits.
• Required to work closely with BU Reliability, Prod, Eng & Design on the design of Life tests schematics & determining Biasing test requirements/conditions
• To continuously drive Reliability cycle time reduction in meeting customer’s expectation while maintaining the expected standard/quality of Reliability services.
• Responsible for verification of Designed Hardware, training of the Line support personnel & working with respective teams , to ensure proper work instruction procedure is in place.
• Preparation of high-quality reports including Engineering DoE and technical insights.
• Work closely with Reliability Engineering & Reliability Requestors to ensure their Reliability Requests are running smoothly and flawlessly to meet their committed expectations.
• To initiate, investigation and respond to Lab induced Qualification failure on a timely basis
• To maintain an effective quality audit, appraisal and reporting system such that deficiencies are reported back to those responsible for immediate corrective actions and Continuous Improvements.(+IATF16949)
• Act as key interface for Rel Lab between Rel Engineering and Requestors of the Reliability requests.
• To monitor regularly that all Reliability Requests are moving per the committed cycle-time at all process steps of the Reliability plans/requests.
• Responsible for assigned RRF requests acceptance ,capacity booking and ONRMS Plan clean-up /changes where necessary
• Work with global reliability labs to support alignment of test methods and lab activities.
• Critique and constructively challenge the approaches taken to resolve design/technical problems and offer alternative solutions where required.
• Other duties as assigned.

Requirements:

• Bachelor’s degree in Electrical/Electronic engineering, Physics or equivalent
• At least +2 years of semiconductor industry experience in Reliability Lab Engineering . Experience in Failure analysis will be advantageous .
• Must have some understanding of basic reliability engineering
• Experience or familiarity with MIL, JEDEC and AECQ, AQG test standards
• Laboratorey Experience in handling Biased Reliability Stresses ( PCT, Dynamic HTOL, HV HTRB, HV H3TRB etc) from design to setup till production release is an advantage
• Understanding of electronic circuits is a must
• Familiarity with statistic software like JMP, Minitab, labview, Autocad is preferred.
• Must be proficient in English and in communication with Global team.
• Skill of analytical, organizational, planning, and problem-solving.
• Individual must be able to multi-task as an individual and in team environments.

onsemi is seeking a self-driven and motivated professional to join the Global Reliability Lab team. As a Senior Engineer , to manage & provide Engineering support for new and existing stress setups of various Reliability tests including providing engineering judgement and reliable Stress data for the stresses run in the lab . He or She will have an opportunity to play a visible and important role in supporting onsemi next-generation power , wide-bandgap and IC products from development, qualification, and production release.