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Salary
$39k – $79k per year (Estimated)
Location
In office (Bengaluru)
Seniority
Staff · 7+ years exp
Overview
Company
Impact
Profile match
Headquartered in Scottsdale, Arizona, Onsemi is a global semiconductor manufacturer specializing in intelligent power and intelligent sensing technologies. The company designs and produces silicon carbide power modules, image sensors, MOSFETs, and mixed-signal integrated circuits engineered for high-efficiency applications. Additionally, it primarily serves the automotive and industrial markets, providing critical hardware for electric vehicle powertrains, advanced driver-assistance systems (ADAS), and renewable energy infrastructure.

OnSemi is seeking a Staff Analog layout Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and e-fuses for consumer, industrial and automotive applications. In this role, you will focus on the following.

Produce high quality layout for complex AMS IP blocks (voltage regulators, bandgap, current sense-amp, amplifier, high voltage switches, drivers etc)

  • Contribute to area estimation and optimization, floor planning, power routing, shielding, physical verification (DRC, ERC, LVS, ESD, etc.), as well power analysis (EM / IR-Drop)
  • Contribute and support team in taping out high-performance microcontroller chip
  • Actively seek out opportunities to work with cross-functional teams (Chip team, Tech, CAD)
  • Develop scripts and methods for layout design automation

BE in Electrical Engineering or related + 7 years of experience, or MS +6 years of experience preferred with experience in analog/mixed-signal layout design of deep submicron CMOS and BCD technologies

Qualification

  • Experience in delivering high quality analog layout IPs
  • Good understanding of layout fundamentals and best practices
  • Proficiency in interpretation of CALIBRE DRC, ERC, LVS, reports
  • Programming knowledge in SKILL, Perl, and/or Python is a bonus
  • Experience with CADENCE or MENTOR GRAPHICS layout tools
  • Solid understanding of semiconductor manufacturing process and DFM techniques
  • Proficient at debugging/fixing LVS/DRC errors
  • Must be familiar with Cadence Design Environment (CDE) and Unix OS
  • Must have strong communication skills and be a team player

#LI-RG1

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