Senior VLSI Verification Engineer

Description

Chips Talk, We Listen

proteanTecs is a game-changing startup that's giving advanced electronics the power to report on their own health. In a digital world built for autonomous driving, cloud computing, and AI, we depend on computing systems daily. But how can we guarantee their safety, reliability and functionality? proteanTecs is the first-ever company to provide visibility into next-gen chips while they are operating, based on the power of on-chip monitoring, machine learning, and data analytics.

Here at proteanTecs, you'll be part of a team that's unlocking deep insights to make electronics more reliable, efficient, and high-quality. We're trusted by industry leaders in data centers, automotive, communications, and consumer devices - we work with the world's largest and most notable companies in tech.

Why proteanTecs is a great place to work:

• Fast-paced and impactful: We're a mission-driven startup, so you'll tackle new challenges daily, wear many hats, and see your work directly influence the future of electronics.
• Supportive company culture: Learn from the best. Our 200+ team members are experts in their field with a proven track record of success, and they're committed to fostering a collaborative and supportive work environment.
• International presence: We're a multinational company with a diverse team across multiple locations around the globe. You'll collaborate on projects with international impact, gaining a global perspective of the tech industry.
• Work with industry leaders: Our solutions are used by the biggest names in tech. You'll be part of the team creating the next generation of groundbreaking products.
• Cutting-edge playground: We use the latest machine learning, platforms, and tools to push boundaries and achieve breakthroughs.
• Real-world impact: Our work keeps data centers, cars, and other critical systems running smoothly. Your work will directly contribute to safer, more reliable electronics.
• We are here for the win: Backed by industry veterans and leading investors, we offer a stable and secure work environment with plenty of room for growth.

proteanTecs is looking for aSenior VLSI Verification Engineer to join the ride as we spearhead the next revolution in electronics!

Requirements

• B.Sc. in Electrical/Computer Engineering or equivalent.
• 5+ years of experience as a VLSI Verification Engineer. Expertise in System-Verilog and UVM.
• Strong software development skills and the ability to develop reusable verification components and utilities.
• Strong organizational and planning skills, with the ability to prioritize and drive verification projects to completion.
• Effective communicator with a structured, detail-oriented approach to problem-solving and collaboration.

Advantages:

• Experience with Git, Python, code templating methods, and open-source verification workflows.
• Familiarity with full-chip level aspects of VLSI verification (reset architecture and sequences, power domains and modes, etc.).
• Experience in firmware verification, including emulation-based verification on FPGA.
• Experience with formal verification or mixed-signal simulation.

Responsibilities

• Develop and maintain advanced verification environments using SystemVerilog and UVM, ensuring scalability, configurability, and reusability across multiple IPs.
• Design, implement, and execute comprehensive testbenches and random test suites to validate functional correctness, robustness, and corner-case behavior of complex IP within various SoC integration environments.
• Drive coverage closure by defining, collecting, and analyzing code and functional coverage metrics; identify verification gaps and ensure complete validation of feature sets prior to sign-off.
• Lead debug and root-cause analysis efforts in collaboration with senior verification and design engineers, leveraging carefully crafted logs, waveform analysis and assertions to isolate and resolve design or environment issues.
• Collaborate closely with architecture, design, and firmware teams to ensure verification completeness, alignment with design intent, and seamless integration at the system level.
• Contribute to methodology and infrastructure improvements, including reusable UVM components, automation scripts, and best practices that enhance team efficiency and verification quality.