CAD Verification Director

Company:

Job Area:

General Summary:

.We are seeking a visionary and technically accomplished Director, Verification CAD Engineer to lead our verification CAD team. This role is pivotal in shaping the strategy, architecture, and execution of verification methodologies that ensure the functional integrity of our cutting-edge silicon designs.

As a senior leader, you will drive innovation in verification flows, mentor a high-performing team, and collaborate across design, verification, and EDA partners to deliver scalable, efficient, and robust CAD solutions.

Key Responsibilities

• Define and execute the long-term roadmap for CAD verification infrastructure supporting both formal and dynamic methodologies.
• Lead and grow a team of CAD engineers focused on verification tooling, automation, and methodology.
• Partner with design and verification leadership to align CAD strategy with project goals and technology trends.
• Architect and deploy formal verification flows including property checking, equivalence checking, and model checking.
• Evaluate and integrate formal tools (e.g., Jasper, VC Formal) into production environments.
• Promote assertion-based verification and formal coverage metrics across design teams.
• Oversee dynamic simulation infrastructure including UVM testbench support, regression automation, and coverage analysis.
• Optimize simulation performance and scalability across compute farms and cloud environments.
• Drive adoption of advanced techniques such as constrained-random testing, functional coverage, and hybrid formal-dynamic flows.
• Develop reusable scripts, APIs, and frameworks to streamline verification workflows.
• Ensure robust version control, CI/CD integration, and tool interoperability.
• Collaborate with EDA vendors to influence tool features and resolve technical challenges.

Required Qualifications

• Bachelor’s or Master’s degree in , Electrical/Electronics Engineering, Computer Engineering, or related field.
• 18+ years of experience in CAD or verification engineering, with significant leadership experience.
• Proven track record in deploying formal and dynamic verification methodologies at scale.
• Expertise in scripting languages (Python, Perl, Tcl) and CAD tool integration.
• Strong understanding of UVM, SystemVerilog assertions, and verification planning.
• Excellent communication, leadership, and cross-functional collaboration skills.
• Familiarity with AI/ML applications in verification and debug.
• Prior experience in managing global teams and multi-site verification initiatives.

Minimum Qualifications:

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

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