RTL Synthesis Methodology Principal Engineer

As the Principal Engineer, RTL Synthesis Methodology Lead, you will drive the technical direction and deployment of next-generation RTL-to-Gate implementation flows for Qualcomm's industry-leading SoCs (Snapdragon Mobile, Automotive, Compute, and IoT). You will lead the definition and optimization of synthesis methodologies to maximize Power, Performance, and Area (PPA) while ensuring robust signoff closure for Synthesis, Low Power, STA, and LEC. You will partner closely with Design teams (CPU, GPU, Modem, DSP), Physical Design (PD) teams, and major EDA vendors (Synopsys, Cadence) to benchmark, certify, and deploy advanced features like Physical Synthesis, Machine Learning-based optimization, and Unified Low Power flows.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.
• OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.
• OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

Key Responsibilities:

• Methodology Leadership: Lead the definition, development, and deployment of the global RTL Synthesis Reference Flow (Fusion Compiler, Genus) across multiple technology nodes (5nm, 3nm, 2nm and beyond).
• PPA Optimization: Drive "RTL2GDS" co-optimization initiatives. Collaborate with RTL and PD teams to deliver measurable PPA improvements through advanced synthesis techniques.
• Low Power Synthesis: Architect and maintain the Low Power (UPF/IEEE 1801) implementation methodology. Drive the flow for Static Low Power checking (CLP/VCLP) and power intent verification from RTL to Netlist.
• Signoff Convergence (STA & LEC): Ownership of Logic Equivalence Checking (LEC) flows (Conformal/Formality) for complex data paths, retiming, and functional ECOs. Drive constraints management and early STA signoff quality (Fishtail, PrimeTime).
• Tool Roadmap & Vendor Engagement: Act as the primary technical interface with EDA vendors (Synopsys, Cadence). Drive tool roadmaps, manage beta evaluations, and file critical enhancements to close gaps between foundry claims and actual product PPA.
• Flow Automation: Oversee the development of scalable, robust automation (Python/Tcl) to integrate synthesis with DFT insertion and Netlist Signoff.
• Mentorship: Mentor a team of CAD engineers, providing technical guidance on complex debugs, flow architecture, and best practices.

Minimum Qualifications:

• Experience: 15+ years of solid experience in ASIC CAD flow development, Physical Design, or Synthesis Methodology.
• Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• Synthesis Expertise: Deep expertise in industry-standard Synthesis tools (Synopsys Fusion Compiler (FC)/Design Compiler (DC-NXT) and Cadence Genus). Proven track record of solving complex PPA challenges.
• Signoff Expertise: Hands-on mastery of Logic Equivalence Checking (LEC) tools (Cadence Conformal LEC, Synopsys Formality) including debug of difficult non-equivalent points in datapath-heavy designs.
• Timing & Constraints: Strong understanding of Static Timing Analysis (STA), SDC constraints generation, and validation (PrimeTime, GCA/Fishtail).
• Scripting: Advanced proficiency in Tcl and Python for flow development and data analysis.

Preferred Qualifications:

• Low Power Synthesis: Deep knowledge of UPF/CPF flows, multi-voltage domains, power gating, retention.
• Physical Awareness: Experience with Physical Synthesis technologies (DEF-based flow, iSpatial, Physical guidance) and correlation with P&R tools (Innovus/ICC2).
• DFT Integration: Familiarity with RTL-integrated DFT flows (Scan stitching, MBIST insertion) and their impact on timing/congestion.
• Leadership: Demonstrated ability to lead cross-site projects, influence design methodologies, and manage stakeholder expectations in a fast-paced environment.
• Innovation: Experience with AI/ML-driven CAD tools (e.g., Fusion.ai, Cerebrus) for design space exploration is a strong plus.

Skills

ASIC, CAD, Python, RTL, Synthesis, Tcl