Senior Lead STA Engineer

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Job Area:

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Minimum Qualifications:

OR

Master's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

Desired experience:

• 5+ years of experience in static timing analysis, constraints and other physical implementation aspects.
• Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc.
• Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths.
• Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs.
• Should be aware about the tricks for minimizing power.
• Experience in deep submicron process technology nodes is strongly preferred.
• Knowledge of high performance and low power implementation methods is preferred.
• Willing to push PPA to the best possible extent.
• Strong fundamentals.
• Expertise in Perl, TCL language

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